第一篇：多功能数字钟课程设计VHDL代码书上程序改
library ieee;use ieee.std_logic_1164.all;entity clock is port(clk1hz:in std_logic;--1hz脉冲--clk100:in std_logic;--100hz脉冲--weekclk:in std_logic;--星期调整脉冲--start_stop:in std_logic;--秒表启动/停止控制--reset:in std_logic;--秒表复位--adclk:in std_logic;--校时脉冲--setselect:in std_logic;--调整位选择脉冲--mode:in std_logic;--功能选择脉冲--showdate:in std_logic;--日期显示--dis:out std_logic_vector(23 downto 0);--显示输出--glisten:out std_logic_vector(5 downto 0);--闪烁指示--weekout:out std_logic_vector(3 downto 0);--星期输出--qh:out std_logic--整点报时--);end clock;architecture arch of clock is component adjust
port（adclk: in std_logic;
data_in: out std_logic_vector(7 downto 0));end component;component control
port（setclk: in std_logic;
setlap: out std_logic_vector(1 downto 0);
mode: in std_logic;
module: out std_logic_vector(2 downto 0));end component;component weekcounter
port（clk: in std_logic;
clk2: in std_logic;
q: out std_logic_vector(3 downto 0));end component;component stopwatch
port（clk: in std_logic;
reset: in std_logic;
start_stop: in std_logic;
centsec: out std_logic_vector(7 downto 0);
sec: out std_logic_vector(7 downto 0);
min: out std_logic_vector(7 downto 0));end component;component h_m_s_count
port（clk: in std_logic;
set: in std_logic;
setlap: in std_logic_vector(1 downto 0);
d:in std_logic_vector(7 downto 0);
sec:out std_logic_vector(7 downto 0);
min:out std_logic_vector(7 downto 0);
hour:out std_logic_vector(7 downto 0);
qh:out std_logic;
qc: out std_logic);end component;component y_m_d_count
port（clk: in std_logic;
set: in std_logic;
setlap: in std_logic_vector(1 downto 0);
data_in: in std_logic_vector(7 downto 0);
day: out std_logic_vector(7 downto 0);
month: out std_logic_vector(7 downto 0);
year: out std_logic_vector(7 downto 0));end component;component display
port（module: in std_logic_vector(2 downto 0);
showdate:in std_logic;
clk:in std_logic;
setlap:in std_logic_vector(1 downto 0);
watch: in std_logic_vector(23 downto 0);
time:in std_logic_vector(23 downto 0);
date:in std_logic_vector(23 downto 0);
dis: out std_logic_vector(23 downto 0);
glisten:out std_logic_vector(5 downto 0));end component;signal data_in,mcentsec,msec,mmin,ssec,smin,shour,sdate,smonth,syear:std_logic_vector(7 downto 0);signal setlap:std_logic_vector(1 downto 0);signal module:std_logic_vector(2 downto 0);signal qc:std_logic;signal watch,time,date:std_logic_vector(23 downto 0);begin u1:adjust port map(adclk,data_in);u2:control port map(setselect,setlap,mode,module);u3:stopwatch port map(clk100,reset,start_stop,mcentsec,msec,mmin);u4:h_m_s_count port map(clk1hz,module(1),setlap,data_in,ssec,smin,shour,qh,qc);u5:y_m_d_count port map(qc,module(2),setlap,data_in,sdate,smonth,syear);u6:display port map(module,showdate,clk1hz,setlap,watch,time,date,dis,glisten);u7:weekcounter port map(qc,weekclk,weekout);watch<=mmin&msec&mcentsec;time<=shour&smin&ssec;date<=syear&smonth&sdate;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity adjust is
port（adclk: in std_logic;
data_in: out std_logic_vector(7 downto 0));end adjust;architecture arch of adjust is signal temp2,temp1:std_logic_vector(3 downto 0);begin process(adclk)begin if rising_edge(adclk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“1001” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;end if;end if;data_in<=temp2&temp1;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity control is
port（setclk: in std_logic;--调整脉冲--
setlap: out std_logic_vector(1 downto 0);--调整位选择脉冲--
mode: in std_logic;--功能选择脉冲--
module: out std_logic_vector(2 downto 0)--功能输出--);end control;architecture arch of control is signal ssetlap:std_logic_vector(1 downto 0);signal s:std_logic_vector(3 downto 0);begin process(mode,setclk)begin if mode='1'then ssetlap<=“00”;elsif rising_edge(setclk)then if ssetlap=“10”then ssetlap<=“00”;else ssetlap<=ssetlap+'1';end if;end if;end process;setlap<=ssetlap;process(mode)begin if rising_edge(mode)then case s is when“0001”=>s<=“0010”;when“0010”=>s<=“0100”;when“0100”=>s<=“1000”;when“1000”=>s<=“0001”;when others=>s<=“0010”;end case;end if;end process;module<=s(3 downto 1);end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity counter60 is
port（clk: in std_logic;--计数脉冲--
clr: in std_logic;--复位--
q: out std_logic_vector(7 downto 0);--计数值--
qc:out std_logic--进位输出--);end counter60;architecture arch of counter60 is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clr,clk)begin if clr='1'then temp1<=“0000”;temp2<=“0000”;elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else temp1<=temp1+'1';end if;if temp2=“0101” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;qc<='1';else qc<='0';end if;end if;q<=temp2&temp1;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity counter99 is
port（clk: in std_logic;--100vhz计数脉冲--
en: in std_logic;--计数使能--
clr: in std_logic;--复位--
q: out std_logic_vector(7 downto 0);--计数值--
qc: out std_logic--进位--);end counter99;
architecture arch of counter99 is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clr,clk)begin if clr='1'then temp1<=“0000”;temp2<=“0000”;elsif rising_edge(clk)then if en='1' then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“1001” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;qc<='1';else qc<='0';end if;end if;end if;q<=temp2&temp1;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity daycounter is
port（clk: in std_logic;--计数脉冲--
set: in std_logic;--调整信号--
day_in: in std_logic_vector(7 downto 0);--调整输入--
day_out: out std_logic_vector(7 downto 0);--天输出--
qc: out std_logic;--进位--
day28: in std_logic;--该位为1表示该月为28天--
day29: in std_logic;--该位为1表示该月为29天--
day30: in std_logic;--该位为1表示该月为30天--
day31: in std_logic--该位为1表示该月为31天--);end daycounter;architecture arch of daycounter is signal temp1,temp2:std_logic_vector(3 downto 0);signal days:std_logic_vector(7 downto 0);begin days<=“00101000” when day28='1'else
“00101001”when day29='1'else
“00110000”when day30='1'else
“00110001”when day31='1'else
“00000000”;process(clk,set,day_in,days)begin if set='1' then temp2<=day_in(7 downto 4);temp1<=day_in(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else temp1<=temp1+'1';end if;if temp2&temp1=days then temp2<=“0000”;temp1<=“0001”;qc<='1';else qc<='0';end if;end if;end process;day_out<=temp2&temp1;end arch;library ieee;use ieee.std_logic_1164.all;entity days_control is port（month: in std_logic_vector(7 downto 0);--月份--
year2: in std_logic;--年份高位数字bcd码最低位--
year1: in std_logic_vector(1 downto 0);--年份低位数字bcd码末两位--
day28: out std_logic;--该位为1表示该月为28天--day29: out std_logic;--该位为1表示该月为29天--
day30: out std_logic;--该位为1表示该月为30天--
day31: out std_logic--该位为1表示该月为31天--);end days_control;architecture arch of days_control is begin process(month,year2,year1)begin case month is when “00000001”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00000010”=>if(year2='0'and year1=“00”)or(year2='1'and year1=“10”)then
day28<='0';day29<='1';day30<='0';day31<='0';
else
day28<='1';day29<='0';day30<='0';day31<='0';
end if;when “00000011”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00000100”=>day28<='0';day29<='0';day30<='1';day31<='0';when “00000101”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00000110”=>day28<='0';day29<='0';day30<='1';day31<='0';when “00000111”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00001000”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00001001”=>day28<='0';day29<='0';day30<='1';day31<='0';when “00010000”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00010001”=>day28<='0';day29<='0';day30<='1';day31<='0';when “00010010”=>day28<='0';day29<='0';day30<='0';day31<='1';when others=>day28<='0';day29<='0';day30<='0';day31<='1';end case;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity display is
port（module: in std_logic_vector(2 downto 0);--功能选择--
showdate:in std_logic;--显示日期--
clk:in std_logic;--闪烁脉冲--
setlap:in std_logic_vector(1 downto 0);--闪烁位选择--
watch: in std_logic_vector(23 downto 0);--秒表计数值输入--
time:in std_logic_vector(23 downto 0);--时分秒计数值输入--date:in std_logic_vector(23 downto 0);--年月日计数值输入--
dis: out std_logic_vector(23 downto 0);--显示输出--
glisten:out std_logic_vector(5 downto 0)--闪烁输出--);end display;architecture arch of display is begin process(module,showdate,watch,time,date)begin if showdate='1'then dis<=date;else case module is when“001”=>dis<=watch;when“010”=>dis<=time;when“100”=>dis<=date;when others=>dis<=time;end case;end if;end process;process(clk,module,setlap)begin if module=“010”or module=“100”then case setlap is when“00”=>glisten(1 downto 0)<=clk&clk;
glisten(5 downto 2)<=“0000”;when“01”=>glisten(3 downto 2)<=clk&clk;
glisten(5 downto 4)<=“00”;
glisten(1 downto 0)<=“00”;when“10”=>glisten(5 downto 4)<=clk&clk;
glisten(3 downto 0)<=“0000”;when others=>glisten<=“000000”;end case;else glisten<=“000000”;end if;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity dmux is
port（set:in std_logic;--调整信号--
setlap: in std_logic_vector(1 downto 0);--调整位选择--
d: in std_logic_vector(7 downto 0);--调整输入--
set1:out std_logic;
set2:out std_logic;
set3:out std_logic;
q1: out std_logic_vector(7 downto 0);
q2: out std_logic_vector(7 downto 0);
q3: out std_logic_vector(7 downto 0));end dmux;architecture arch of dmux is begin process(set,setlap,d)begin if set='1' then case setlap is when“00”=>set1<='1';set2<='0';set3<='0';
q1<=d;when“01”=>set1<='0';set2<='1';set3<='0';
q2<=d;when“10”=>set1<='0';set2<='0';set3<='1';
q3<=d;when others=>set1<='0';set2<='0';set3<='0';end case;else set1<='0';set2<='0';set3<='0';end if;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity h_m_s_count is
port（clk: in std_logic;--1hz脉冲--
set: in std_logic;--调整信号--
setlap: in std_logic_vector(1 downto 0);--调整位选择--
d:in std_logic_vector(7 downto 0);--调整输入--
sec:out std_logic_vector(7 downto 0);--秒输出--
min:out std_logic_vector(7 downto 0);--分输出--
hour:out std_logic_vector(7 downto 0);--小时输出--
qh:out std_logic;--整点报时--
qc: out std_logic--进位--);end h_m_s_count;architecture arch of h_m_s_count is component sec_mincounter
port（clk: in std_logic;
set:in std_logic;
d:in std_logic_vector(7 downto 0);
q:out std_logic_vector(7 downto 0);
qc:out std_logic);end component;component hourcounter port（clk: in std_logic;
set:in std_logic;
d:in std_logic_vector(7 downto 0);
q: out std_logic_vector(7 downto 0);
qc:out std_logic);end component;component dmux
port（set:in std_logic;
setlap: in std_logic_vector(1 downto 0);
d: in std_logic_vector(7 downto 0);
set1:out std_logic;
set2:out std_logic;
set3:out std_logic;
q1: out std_logic_vector(7 downto 0);
q2: out std_logic_vector(7 downto 0);
q3: out std_logic_vector(7 downto 0));end component;signal secset,minset,hourset: std_logic;signal secin,minin,hourin:std_logic_vector(7 downto 0);signal qcsec,qcmin,qchour: std_logic;begin u1:dmux port map(set,setlap,d,secset,minset,hourset,secin,minin,hourin);u2:sec_mincounter port map(clk,secset,secin,sec,qcsec);u3:sec_mincounter port map(qcsec,minset,minin,min,qcmin);u4:hourcounter port map(qcmin,hourset,hourin,hour,qchour);qh<=qcmin;qc<=qchour;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity hourcounter is
port（clk: in std_logic;--计数脉冲--
set:in std_logic;--调整信号--
d:in std_logic_vector(7 downto 0);--调整时间--
q: out std_logic_vector(7 downto 0);--小时输出--
qc:out std_logic--进位--);end hourcounter;architecture arch of hourcounter is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clk,set)begin if set='1'then temp2<=d(7 downto 4);temp1<=d(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“0010” and temp1=“0100” then temp1<=“0000”;temp2<=“0000”;qc<='1';else qc<='0';end if;end if;end process;q<=temp2&temp1;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity monthcounter is
port（clk: in std_logic;--计数脉冲--
set: in std_logic;--调整信号--
month_in: in std_logic_vector(7 downto 0);--调整输入--
month_out: out std_logic_vector(7 downto 0);--月输出--
qc: out std_logic--进位--);end monthcounter;architecture arch of monthcounter is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clk,set,month_in)begin if set='1' then temp2<=month_in(7 downto 4);temp1<=month_in(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“0001”and temp1=“0010” then temp2<=“0000”;temp1<=“0001”;qc<='1';else qc<='0';end if;end if;end process;month_out<=temp2&temp1;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity sec_mincounter is port（clk: in std_logic;--计数脉冲--
set:in std_logic;--调整信号--
d:in std_logic_vector(7 downto 0);--调整时间输入--
q:out std_logic_vector(7 downto 0);--分和秒输出--
qc:out std_logic--进位--);end sec_mincounter;architecture arch of sec_mincounter is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clk,set)begin if set='1'then temp2<=d(7 downto 4);temp1<=d(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“0101” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;qc<='1';else qc<='0';end if;end if;end process;q<=temp2&temp1;end arch;library ieee;use ieee.std_logic_1164.all;entity stopwatch is port（clk: in std_logic;--100hz脉冲--
reset: in std_logic;--复位--
start_stop: in std_logic;--启动/停止--
centsec: out std_logic_vector(7 downto 0);--百分秒输出，当超过60分转为秒--
sec: out std_logic_vector(7 downto 0);--秒输出，当超过60分转为分--
min: out std_logic_vector(7 downto 0)--分输出，当超过60分转为小时--);end stopwatch;architecture arch of stopwatch is component counter99 port（clk: in std_logic;
en: in std_logic;
clr: in std_logic;
q: out std_logic_vector(7 downto 0);
qc: out std_logic);end component;component counter60 port（clk: in std_logic;
clr: in std_logic;
q: out std_logic_vector(7 downto 0);
qc: out std_logic);end component;signal qc1,qc2,qc3,qc4,flag:std_logic;signal tcentsec,tsec,tmin,thour:std_logic_vector(7 downto 0);begin u1:counter99 port map(clk,start_stop,reset,tcentsec,qc1);u2:counter60 port map(qc1,reset,tsec,qc2);u3:counter60 port map(qc2,reset,tmin,qc3);u4:counter60 port map(qc3,reset,thour,qc4);process(qc3)begin if rising_edge(qc3)then flag<='1';end if;if flag='1' then centsec<=tsec;sec<=tmin;min<=thour;else centsec<=tcentsec;sec<=tsec;min<=tmin;end if;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity weekcounter is
port（clk: in std_logic;--天脉冲--
clk2: in std_logic;--外部星期调整脉冲--
q: out std_logic_vector(3 downto 0)--星期输出--);end weekcounter;architecture arch of weekcounter is signal temp:std_logic_vector(3 downto 0);signal cp:std_logic;begin cp<=clk or clk2;process begin wait until rising_edge(cp);if temp=“0111” then temp<=“0001”;else
temp<=temp+'1';end if;q<=temp;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity y_m_d_count is
port（clk: in std_logic;--计数脉冲--
set: in std_logic;--调整信号--
setlap: in std_logic_vector(1 downto 0);--调整位选择--
data_in: in std_logic_vector(7 downto 0);--调整输入--
day: out std_logic_vector(7 downto 0);--日输出--
month: out std_logic_vector(7 downto 0);--月输出--
year: out std_logic_vector(7 downto 0)--年输出--);end y_m_d_count;architecture arch of y_m_d_count is component daycounter
port（clk: in std_logic;
set: in std_logic;
day_in: in std_logic_vector(7 downto 0);
day_out: out std_logic_vector(7 downto 0);
qc: out std_logic;
day28: in std_logic;
day29: in std_logic;
day30: in std_logic;
day31: in std_logic);end component;component monthcounter
port（clk: in std_logic;
set: in std_logic;
month_in: in std_logic_vector(7 downto 0);
month_out: out std_logic_vector(7 downto 0);
qc: out std_logic);end component;component yearcounter
port（clk: in std_logic;
set: in std_logic;
year_in: in std_logic_vector(7 downto 0);
year_out: out std_logic_vector(7 downto 0));end component;component dmux
port（set:in std_logic;
setlap: in std_logic_vector(1 downto 0);
d: in std_logic_vector(7 downto 0);
set1:out std_logic;
set2:out std_logic;
set3:out std_logic;
q1: out std_logic_vector(7 downto 0);
q2: out std_logic_vector(7 downto 0);
q3: out std_logic_vector(7 downto 0));end component;component days_control
port（month: in std_logic_vector(7 downto 0);
year2: in std_logic;
year1: in std_logic_vector(1 downto 0);
day28: out std_logic;
day29: out std_logic;
day30: out std_logic;
day31: out std_logic);end component;signal dayset,monthset,yearset: std_logic;signal qcday,qcmonth: std_logic;signal dayin,monthin,yearin: std_logic_vector(7 downto 0);signal smonth,syear:std_logic_vector(7 downto 0);signal day28,day29,day30,day31:std_logic;begin u1:dmux port map(set,setlap,data_in,dayset,monthset,yearset,dayin,monthin,yearin);u2:daycounter port map(clk,dayset,dayin,day,qcday,day28,day29,day30,day31);u3:monthcounter port map(qcday,monthset,monthin,smonth,qcmonth);u4:yearcounter port map(qcmonth,yearset,yearin,syear);u8:days_control port map(smonth,syear(4),syear(1 downto 0),day28,day29,day30,day31);month<=smonth;year<=syear;
end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity yearcounter is
port（clk: in std_logic;--计数脉冲--
set: in std_logic;--调整信号--
year_in: in std_logic_vector(7 downto 0);--调整输入--
year_out: out std_logic_vector(7 downto 0)--年输出--);end yearcounter;architecture arch of yearcounter is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clk,set,year_in)begin if set='1' then temp2<=year_in(7 downto 4);temp1<=year_in(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“1001” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;end if;end if;end process;year_out<=temp2&temp1;end arch;
第二篇：用状态机实现的EDA多功能数字钟课程设计VHDL代码
设计并实现具有一定功能的数字钟
1、该数字钟可以实现3个功能：计时功能、整点报时功能和重置时间功能，因此有3个功能：计时、重置时间、复位。
2、对所有设计的小系统能够正确分析；
3、基于VHDL语言描述系统的功能；
4、在quartus 2环境中编译通过；
5、仿真通过并得到正确的波形；
6、给出相应的设计报告。
其中计时模块有4部分构成：秒计时器（second）、分计时器(minute)、时计时器(hour)、日计时器(date)、月计时器（mouth）、年计时器（year）
1）秒计时器（second）是由一个60进制的计数器构成的，具有清0、置数和计数功能。其中reset为清0信号，当reset为0时，秒计时器清0；set 为置数信号，当set为0时，秒计时器置数，置s1的值。clk为驱动秒计时器的时钟，sec为秒计时器的输出，ensec为秒计时器的进位信号，作为下一级的时钟输入信号。
2）分计时器（minute）是由一个60进制的计数器构成的，具有清0、置数和计数功能。其中reset为清0信号，当reset为0时，分计时器清0；set 为置数信号，当set为0时，分计时器置数，置m1的值。clkm为驱动分计时器工作的时钟，与ensec相连接；min为分计时器的输出；enmin为分计时器的进位信号，作为下一级的时钟输入信号。
3）时计时器（hour）是由一个24进制的计数器构成的，具有清0、置数和计数功能。其中reset为清0信号，当reset为0时，时计时器清0；set 为置数信号，当set为0时，时计时器置数，置h1的值。clkh为驱动时计时器工作的时钟，与enmin相连接；hour为时计时器的输出；enhour为时计时器的进位信号，作为下一级的时钟输入信号。
4）日计时器（date1）是由一个60进制的计数器构成的，具有清0、置数和计数功能。其中reset为清0信号，当reset为0时，星期计时器清0；set 为置数信号，当set为0时，星期计时器置数，置d1的值。clkd为驱动星期计时器工作的时钟，与enhour相连接；date为日计时器的输出，endate为分计时器的进位信号，作为下一级的时钟输入信号，由于月份的天数存在天数不同，闰年2月的天数为28天等情况，还设计了一个润年判别器，准确显示时间。
5）月计时器（mouth）是由一个60进制的计数器构成的，具有清0、置数和计数功能。其中reset为清0信号，当reset为0时，星期计时器清0；set 为置数信号，当set为0时，星期计时器置数，置mou1的值，clkmou为驱动星期计时器工作的时钟，与enday相连接；mou为日计时器的输出，enmou为分计时器的进位信号，作为下一级的时钟输入信号。6）计时器（year）是由一个60进制的计数器构成的，具有清0、置数和计数功能。其中reset为清0信号，当reset为0时，星期计时器清0；set 为置数信号，当set为0时，星期计时器置数，置y1的值，clky为驱动星期计时器工作的时钟，与enmou相连接；year为日计时器的输出。VHDL程序
1、屏幕切换模块
运用状态机进行屏幕切换，分别显示年月日，以及时分秒 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity mux3 is
Port(clk,Reset,sel : in std_logic;
int1,int2,int3,int4,int5,int6,int7,int8,int9,int10,int11,int12:IN STD_LOGIC_VECTOR(3 DOWNTO 0);--rst must
a1,a2,a3,a4,a5,a6: out std_logic_vector(3 downto 0));end mux3;
architecture Behavioral of mux3 is
TYPE states IS(st0, st1, st2, st3, st4, st5, st6, st7);
SIGNAL STX: states;
begin
COM1 : PROCESS(STX,int1,int2,int3,int4,int5,int6,int7,int8,int9,int10,int11,int12)
BEGIN--决定转换状态的进程
CASE STX IS
WHEN st0 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;
WHEN st1 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;
WHEN st2 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;
WHEN st3 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;
WHEN st4 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;
WHEN st5 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;
WHEN st6 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;
WHEN st7 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;
WHEN OTHERS => NULL;
END CASE;
END PROCESS COM1;REG: PROCESS(clk,Reset,sel)
--主控时序进程
BEGIN
IF Reset = '1' THEN
STX<= st0;
--异步复位
ELSIF clk='1' AND clk'EVENT THEN
if sel='1' then
CASE STX IS
WHEN st0=>STX<=st1;
WHEN st1=>STX<=st2;
WHEN st2=>STX<=st3;
WHEN st3=>STX<=st4;
WHEN st4=>STX<=st5;
WHEN st5=>STX<=st6;
WHEN st6=>STX<=st7;
WHEN st7=>STX<=st0;
END CASE;
END IF;
END if;END PROCESS;
2、显示切换程序 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity mux1 is
Port(clk,ina,inb,sel,Reset : in std_logic;
result : out std_logic);end mux1;
architecture Behavioral of mux1 is
TYPE state IS(st0,st1,st2,st3,st4,st5,st6,st7);
SIGNAL STX:state;begin REG1: PROCESS(ina,inb,STX)
BEGIN
CASE STX IS
WHEN st0=>result<=ina;
WHEN st1=>result<=ina;
WHEN st2=>result<=inb;
WHEN st3=>result<=inb;
WHEN st4=>result<=inb;
WHEN st5=>result<=inb;
WHEN st6=>result<=inb;
WHEN st7=>result<=inb;
END CASE;
END PROCESS;REG2:PROCESS(clk,sel,Reset)BEGIN IF(Reset='1')THEN
STX<=st0;ELSIF(clk'EVENT AND clk='1')THEN
if sel='1' then CASE STX IS WHEN st0=>STX<=st1;WHEN st1=>STX<=st2;WHEN st2=>STX<=st3;WHEN st3=>STX<=st4;WHEN st4=>STX<=st5;WHEN st5=>STX<=st6;WHEN st6=>STX<=st7;WHEN st7=>STX<=st0;
END CASE;END IF;end if;END PROCESS REG2;
end Behavioral;
3、置数操作模块
运用状态机，进行置数操作 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity mux is
Port(clk,ina,inb,sel,Reset : in std_logic;
r1,r2,r3,r4,r5,r6 : out std_logic);end mux;
architecture Behavioral of mux is TYPE state IS(st0,st1,st2,st3,st4,st5,st6,st7);
SIGNAL STX:state;begin PROCESS(ina,inb,STX)BEGIN CASE STX IS WHEN st0=>r1<=ina;r2<='0';r3<='0';r4<='0';r5<='0';r6<='0';WHEN st1=>r1<=ina;r2<='0';r3<='0';r4<='0';r5<='0';r6<='0';WHEN st2=>r1<='0';r2<='0';r3<='0';r4<='0';r5<='0';r6<=inb;WHEN st3=>r1<='0';r2<='0';r3<='0';r4<='0';r5<=inb;r6<='0';WHEN st4=>r1<='0';r2<='0';r3<='0';r4<=inb;r5<='0';r6<='0';WHEN st5=>r1<='0';r2<='0';r3<=inb;r4<='0';r5<='0';r6<='0';WHEN st6=>r1<='0';r2<=inb;r3<='0';r4<='0';r5<='0';r6<='0';WHEN st7=>r1<=inb;r2<='0';r3<='0';r4<='0';r5<='0';r6<='0';END CASE;END PROCESS;PROCESS(clk,sel,Reset)BEGIN IF(Reset='1')THEN STX<=st0;ELSIF(clk'EVENT AND clk='1')THEN if sel='1' then CASE STX IS WHEN st0=>STX<=st1;WHEN st1=>STX<=st2;WHEN st2=>STX<=st3;WHEN st3=>STX<=st4;WHEN st4=>STX<=st5;WHEN st5=>STX<=st6;WHEN st6=>STX<=st7;WHEN st7=>STX<=st0;
END CASE;END IF;end if;END PROCESS;end Behavioral;end Behavioral;
4、秒显示模块 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity secute1 is
Port(clkm,set,reset : in std_logic;
sec2,sec1 : inout std_logic_vector(3 downto 0);
ensec : out std_logic);end secute1;
architecture Behavioral of secute1 is
begin
Process(clkm,reset,set)
Begin
If reset='1' then sec2<=“0000”;sec1<=“0000”;
Elsif set='1' then sec2<=“0101”;sec1<=“1000”;
Elsif(clkm'event and clkm='1')then
if sec2=“0101” AND sec1=“1001” then sec2<=“0000”;sec1<=“0000”;ensec<='1';
elsif sec1=“1001” then sec2<=sec2+'1';sec1<=“0000”;ensec<='0';
else sec1<=sec1+'1';ensec<='0';
end if;end if;End process;end Behavioral;
5、分显示模块 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity minute1 is
Port(clkm,set,reset : in std_logic;
min2,min1 : inout std_logic_vector(3 downto 0);
enmin : out std_logic);end minute1;
architecture Behavioral of minute1 is
begin
Process(clkm,reset,set)
Begin
If reset='1' then min2<=“0000”;min1<=“0000”;
Elsif set='1' then min2<=“0101”;min1<=“1000”;
Elsif(clkm'event and clkm='1')then
if min2=“0101” AND min1=“1001” then min2<=“0000”;min1<=“0000”;enmin<='1';
elsif min1=“1001” then min2<=min2+'1';min1<=“0000”;enmin<='0';
else min1<=min1+'1';enmin<='0';
end if;end if;End process;end Behavioral;
6、小时显示模块 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity hour1 is
Port(clkh,set,reset: in std_logic;
hor2,hor1 : inout std_logic_vector(3 downto 0);
enhour : out std_logic);end hour1;
architecture Behavioral of hour1 is
begin Process(clkh,reset,set)
Begin
If reset='1' then hor2<=“0000”;hor1<=“0000”;
Elsif set='1' then hor2<=“0010”;hor1<=“0011”;
Elsif(clkh'event and clkh='1')then
if hor2=“0010” AND hor1=“0011” then hor2<=“0000”;hor1<=“0000”;enhour<='1';
elsif hor1=“1001” then hor2<=hor2+'1';hor1<=“0000”;enhour<='0';
else hor1<=hor1+'1';enhour<='0';
end if;
end if;End process;end Behavioral;
7、日显示模块（已加入闰年判断功能）library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity date1 is
Port(clkd,set : in std_logic;
dat2,dat1 : inout std_logic_vector(3 downto 0);
endate : out std_logic);end date1;
architecture Behavioral of date1 is
begin
Process(clkd,set)
Begin
if set='1' then dat2<=“0010”;dat1<=“1000”;
Elsif(clkd'event and clkd='1')then
if dat2=“0011” AND dat1=“0000” then dat2<=“0000”;dat1<=“0001”;endate<='1';elsif dat1=“1001” then dat2<=dat2+'1';dat1<=“0000”;endate<='0';
else dat1<=dat1+'1';endate<='0';
end if;end if;End process;end Behavioral;
8、月显示模块 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity month1 is
Port(clkn,set: in std_logic;
mon2,mon1 : inout std_logic_vector(3 downto 0);
enmon : out std_logic);end month1;
architecture Behavioral of month1 is
begin
Process(clkn,set)
Begin
if set='1' then mon2<=“0000”;mon1<=“0110”;
Elsif(clkn'event and clkn='1')then
if mon2=“0001” AND mon1=“0010” then mon2<=“0000”;mon1<=“0001”;enmon<='1';
elsif mon1=“1001” then mon2<=mon2+'1';mon1<=“0000”;enmon<='0';
else mon1<=mon1+'1';enmon<='0';
end if;end if;End process;
9、年显示模块 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity yearth1 is
Port(clkn,set: in std_logic;
year2,year1 : inout std_logic_vector(3 downto 0);
enyear : out std_logic);end yearth1;
architecture Behavioral of yearth1 is
begin
Process(clkn,set)
Begin
if set='1' then year2<=“0001”;year1<=“0001”;
Elsif(clkn'event and clkn='1')then
if year2=“1001” AND year1=“1001” then year2<=“0000”;year1<=“0001”;
elsif year1=“1001” then year2<=year2+'1';year1<=“0000”;enyear<='0';
else year1<=year1+'1';enyear<='0';
end if;end if;
end Behavioral;
第三篇：多功能数字钟课程设计整点报时与闹钟功能VHDL代码
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity timkeeper is
Port(up,setpin,upclk,settime,run : in std_logic;
a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0);
result: out std_logic);end timkeeper;
architecture Behavioral of timkeeper is
component h_m_s_time port（clk0,clk1,ce : in std_logic;
sec0,sec1 : buffer std_logic_vector(3 downto 0);
lock : in std_logic_vector(2 downto 0);
up : in std_logic;min0,min1 : buffer std_logic_vector(3 downto 0);hour0,hour1 : buffer std_logic_vector(3 downto 0);ov : out std_logic);end component;component date port（clk0,clk1,ce : in std_logic;
lock : in std_logic_vector(2 downto 0);
up : in std_logic;
mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);
date0,date1 : buffer std_logic_vector(3 downto 0);
ov : out std_logic);
end component;component month_year port（clk0,clk1,ce : in std_logic;
lock : in std_logic_vector(2 downto 0);
up : in std_logic;
mon0,mon1 : buffer std_logic_vector(3 downto 0);
year0,year1 : buffer std_logic_vector(3 downto 0));end component;component LED_disp port（lock : in std_logic_vector(2 downto 0);
sec0,sec1,min0,min1,hour0,hour1 : in std_logic_vector(3 downto 0);
date0,date1,mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);
a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0));end component;component alarm Port（hour1,hour0,min1,min0,sec1,sec0 : in std_logic_vector(3 downto 0);
settime,run : in std_logic;
result : out std_logic);end component;
signal Tlock:std_logic_vector(2 downto 0);signal Tsecond_wave:std_logic;signal Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1:std_logic_vector(3 downto 0);signal Tdate0,Tdate1,Tmon0,Tmon1,Tyear0,Tyear1:std_logic_vector(3 downto 0);signal Tovday,Tovmonth:std_logic;signal vcc:std_logic;begin vcc<='1';process(setpin)begin
if rising_edge(setpin)then
Tlock<=Tlock+'1';
end if;
end process;
u2:h_m_s_time port map(Tsecond_wave,upclk,vcc,Tsec0,Tsec1,Tlock,up，Tmin0,Tmin1,Thour0,Thour1,Tovday);u3:date port map(Tovday,upclk,vcc,Tlock,up,Tmon0,Tmon1,Tyear0,Tyear1，Tdate0,Tdate1,Tovmonth);u4:month_year port map(Tovmonth,upclk,vcc,Tlock,up,Tmon0,Tmon1,Tyear0,Tyear1);u5:LED_disp port map(Tlock,Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1,Tdate0，Tdate1,Tmon0,Tmon1,Tyear0,Tyear1,a0,a1,b0,b1,c0,c1);u6:alarm port map(Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1,settime,run ,result);end Behavioral;
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;use work.pac.all;entity alarm is
Port(hour1,hour0,min1,min0,sec1,sec0 : in std_logic_vector(3 downto 0);
settime,run : in std_logic;
result : out std_logic);end alarm;
architecture Behavioral of alarm is signal dhour1,dhour0,dmin1,dmin0,dsec1,dsec0:std_logic_vector(3 downto 0);begin p0:process(settime)
begin
if settime='1'then
dhour1<=hour1;
dhour0<=hour0;
dmin1<=min1;
dmin0<=min0;
dsec1<=sec1;
dsec0<=sec0;
end if;
end process p0;p1:process(run)
begin if run='1'then
if hour1=dhour1 and hour0=dhour0 and min1=dmin1 and min0=dmin0 and sec1=dsec1 and sec0 =dsec0 then
result<='1';
else result<='0';
end if;else result<='0';end if;
end process p1;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;use work.pac.all;entity date is
Port(clk0,clk1,ce : in std_logic;
lock : in std_logic_vector(2 downto 0);
up : in std_logic;
mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);
date0,date1 : buffer std_logic_vector(3 downto 0);
ov : out std_logic);end date;
architecture Behavioral of date is signal tempy0:std_logic_vector(1 downto 0);signal tempy1,clk:std_logic;signal Td0,Td1:std_logic_vector(3 downto 0);begin tempy0<=year0(1 downto 0);tempy1<=year1(0);Td0<=date0;Td1<=date1;u1:process(lock,clk0,clk1)
begin
if(lock=“000” or lock=“001”)then clk<=clk0;
else clk<=clk1;
end if;
end process u1;
u2:process(clk,ce)
begin
if rising_edge(clk)then
if(ce='1')then
if(lock=“000”)or(lock=“001”)or(lock=“100” and up='1')then
if(mon0=“0010” and mon1=“0000”)then
Feb_add_day(Td0,Td1,tempy0,tempy1,date0,date1);
elsif((mon0=“0001” and mon1=“0000”)or(mon0=“0011” and or(mon0=“0101” and mon1=“0000”)or(mon0=“0111” and mon1=“0000”)
mon1=“0000”)
or(mon0=“1000” and mon1=“0000”)or(mon0=“0000”and mon1=“0001”)or(mon0=“0010” and mon1=“0001”))then
oddmonth_add_day(Td0,Td1,date0,date1);
else evenmonth_add_day(Td0,Td1,date0,date1);
end if;
end if;
if(lock=“100” and up='0')then
if(mon0=“0010” and mon1=“0000”)then
Feb_sub_day(Td0,Td1,tempy0,tempy1,date0,date1);
elsif((mon0=“0001” and mon1=“0000”)or(mon0=“0011” and mon1=“0000”)or(mon0=“0101” and mon1=“0000”)or
(mon0=“0111” and mon1=“0000”)or(mon0=“1000” and mon1=“0000”)or(mon0=“0000” and mon1=“0001”)or(mon0=“0010”
and mon1=“0001”))then
oddmonth_sub_day(Td0,Td1,date0,date1);
else evenmonth_sub_day(Td0,Td1,date0,date1);
end if;
end if;
end if;
end if;
end process u2;
u3:process(ce)
begin
if rising_edge(clk)then
if(lock/=“000” and lock/=“001”)then
ov<='0';
elsif(ce='1')then
if(mon0=“0010” and mon1=“0000”)then
if((tempy1='0' and tempy0=“00”)or(tempy1='1' and tempy0=“10”))then
if(date0=“1001” and date1=“0010”)then
ov<='1';
else ov<='0';
end if;
elsif(date0=“1000” and date1=“0010”)then ov<='1';else ov<='0';end if;
elsif((mon0=“0001” and mon1=“0000”)or(mon0=“0011” and mon1=“0000”)or(mon0=“0010” and mon1=“0000”)
or(mon0=“0111” and mon1=“0000”)or(mon0=“1000” or(mon0=“0000” and mon1=“0001”)
or(mon0=“0010” and mon1=“0001”))then
if(date0=“0001” and date1=“0011”)then
ov<='1';
else ov<='0';
end if;
elsif(date0=“0000” and date1=“0011”)then
ov<='1';
else ov<='0';
end if;
end if;
end if;
end process u3;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;
and
mon1=“0000”)use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;use work.pac.all;entity h_m_s_time is
Port(clk0,clk1,ce : in std_logic;
sec0,sec1 : buffer std_logic_vector(3 downto 0);
lock : in std_logic_vector(2 downto 0);
up : in std_logic;
min0,min1 : buffer std_logic_vector(3 downto 0);
hour0,hour1 : buffer std_logic_vector(3 downto 0);
ov : out std_logic);end h_m_s_time;
architecture Behavioral of h_m_s_time is signal Ts0,Ts1,Tm0,Tm1,Th0,Th1:std_logic_vector(3 downto 0);signal clk:std_logic;begin
Ts0<=sec0;Ts1<=sec1;Tm0<=min0;Tm1<=min1;Th0<=hour0;Th1<=hour1;u1: process(lock,clk0,clk1)
begin
if(lock=“000” or lock=“001”)then
clk<=clk0;
else clk<=clk1;
end if;
end process u1;
u2: process(clk,lock)
begin
if rising_edge(clk)then
if(ce='1')then
if(lock=“000”)or(lock=“001”)or(lock=“111” and up='1')then
addsec_addmin(Ts0,Ts1,sec0,sec1);
end if;
if(lock=“111” and up='0')then
subsec_submin(Ts0,Ts1,sec0,sec1);
end if;
if(lock=“000” or lock=“001”)then
if(sec0=“1001” and sec1=“0101”)then
addsec_addmin(Tm0,Tm1,min0,min1);
end if;
if(sec0=“1001” and sec1=“0101” and min0=“1001” and min1=“0101”)then
addhour(Th0,Th1,hour0,hour1);
end if;
if(sec0=“1001” and sec1=“0101” and min0=“1001” and min1=“0101”
and hour0=“0011” and hour1=“0010”)then
ov<='1';
else ov<='0';
end if;
end if;
if(lock=“110” and up='1')then
addsec_addmin(Tm0,Tm1,min0,min1);
end if;
if(lock=“101” and up='0')then
subsec_submin(Tm0,Tm1,min0,min1);
end if;
if(lock=“101” and up='1')then
addhour(Th0,Th1,hour0,hour1);
end if;
if(lock=“101” and up='0')then
subhour(Th0,Th1,hour0,hour1);
end if;
end if;
end if;
end process u2;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity LED_disp is
Port(lock : in std_logic_vector(2 downto 0);
sec0,sec1,min0,min1,hour0,hour1 : in std_logic_vector(3 downto 0);
date0,date1,mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);
a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0));end LED_disp;
architecture Behavioral of LED_disp is begin process(lock,sec0,sec1,min0,min1,hour0,hour1,date0,date1,mon0,mon1,year0,year1)
begin
if(lock=“000”)then
a0<=sec0;a1<=sec1;b0<=min0;b1<=min1;c0<=hour0;c1<=hour1;
end if;
if(lock=“000”)then
a0<=sec0;a1<=sec1;b0<=min0;b1<=min1;c0<=hour0;c1<=hour1;
end if;
if(lock=“001”)then
a0<=date0;a1<=date1;b0<=mon0;b1<=mon1;c0<=year0;c1<=year1;
end if;
if(lock=“101”)then
a0<=“0000”;a1<=“0000”;b0<=“0000”;b1<=“0000”;c0<=hour0;c1<=hour1;
end if;
if(lock=“110”)then
a0<=“0000”;a1<=“0000”;b0<=min0;b1<=min1;c0<=“0000”;c1<=“0000”;
end if;
if(lock=“111”)then
a0<=sec0;a1<=sec1;b0<=“0000”;b1<=“0000”;c0<=“0000”;c1<=“0000”;
end if;
if(lock=“010”)then a0<=“0000”;a1<=“0000”;b0<=“0000”;b1<=“0000”;c0<=year0;c1<=year1;end if;if(lock=“011”)then
a0<=“0000”;a1<=“0000”;b0<=mon0;b1<=mon1;c0<=“0000”;c1<=“0000”;
end if;
if(lock=“100”)then
a0<=date0;a1<=date1;b0<=“0000”;b1<=“0000”;c0<=“0000”;c1<=“0000”;
end if;
end process;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;use work.pac.all;entity month_year is
Port(clk0,clk1,ce : in std_logic;
lock : in std_logic_vector(2 downto 0);
up : in std_logic;
mon0,mon1 : buffer std_logic_vector(3 downto 0);
year0,year1 : buffer std_logic_vector(3 downto 0));end month_year;
architecture Behavioral of month_year is signal Ty0,Ty1,Tm0,Tm1:std_logic_vector(3 downto 0);signal clk:std_logic;begin
Ty0<=year0;Ty1<=year1;Tm0<=mon0;Tm1<=mon1;u1: process(lock,clk0,clk1)
begin
if(lock=“000” or lock=“001”)then
clk<=clk0;
else clk<=clk1;
end if;
end process u1;u2:process(clk,ce)begin if rising_edge(clk)then
if(ce='1')then
if(lock=“000”)or(lock=“001”)or(lock=“011” and up='1')then
add_month(Tm0,Tm1,mon0,mon1);
end if;
if(lock=“011” and up='0')then
sub_month(Tm0,Tm1,mon0,mon1);
end if;
if(lock=“000” or lock=“001”)then
if(mon0=“0010” and mon1=“0001”)then
add_year(Ty0,Ty1,year0,year1);
end if;
end if;
if(lock=“010” and up='1')then
add_year(Ty0,Ty1,year0,year1);
end if;
if(lock=“010” and up='0')then
sub_year(Ty0,Ty1,year0,year1);
end if;
end if;
end if;
end process u2;
end Behavioral;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
package pac is
procedure add_year(oldyear0,oldyear1:in std_logic_vector;
signal newyear0:out std_logic_vector;
signal newyear1:out std_logic_vector);procedure add_month(oldmonth0,oldmonth1:in std_logic_vector;
signal newmonth0:out std_logic_vector;
signal newmonth1:out std_logic_vector);procedure sub_month(oldmonth0,oldmonth1:in std_logic_vector;
signal newmonth0:out std_logic_vector;
signal newmonth1:out std_logic_vector);procedure sub_year(oldyear0,oldyear1:in std_logic_vector;
signal newyear0:out std_logic_vector;
signal newyear1:out std_logic_vector);procedure Feb_add_day(oldday0,oldday1:in std_logic_vector;
ty0:in std_logic_vector(1 downto 0);
ty1:in std_logic;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure Feb_sub_day(oldday0,oldday1:in std_logic_vector;
ty0:in std_logic_vector(1 downto 0);
ty1:in std_logic;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure oddmonth_add_day(oldday0,oldday1:in std_logic_vector;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure oddmonth_sub_day(oldday0,oldday1:in std_logic_vector;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure evenmonth_add_day(oldday0,oldday1:in std_logic_vector;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure evenmonth_sub_day(oldday0,oldday1:in std_logic_vector;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure addsec_addmin(oldtime0,oldtime1:in std_logic_vector;
signal newtime0:out std_logic_vector;
signal newtime1:out std_logic_vector);procedure subsec_submin(oldtime0,oldtime1:in std_logic_vector;
signal newtime0:out std_logic_vector;
signal newtime1:out std_logic_vector);procedure addhour(oldhour0,oldhour1:in std_logic_vector;
signal newhour0:out std_logic_vector;
signal newhour1:out std_logic_vector);procedure subhour(oldhour0,oldhour1:in std_logic_vector;
signal newhour0:out std_logic_vector;
signal newhour1:out std_logic_vector);end pac;package body pac IS procedure add_year(oldyear0,oldyear1:in std_logic_vector;
signal newyear0:out std_logic_vector;
signal newyear1:out std_logic_vector)is
begin
if(oldyear0=“1001” and oldyear1/=“1001”)then
newyear0<=“0000”;newyear1<=oldyear1+'1';
else newyear0<=oldyear0+'1';
end if;if oldyear0=“1001” and oldyear1=“1001” then newyear0<=“0000”;
newyear1<=“0000”;end if;end add_year;
procedure add_month(oldmonth0,oldmonth1:in std_logic_vector;
signal newmonth0:out std_logic_vector;
signal newmonth1:out std_logic_vector)is
begin
if oldmonth0=“0010” and oldmonth1=“0001” then newmonth0<=“0001”;
newmonth1<=“0000”;
elsif oldmonth0=“1001” then newmonth0<=“0000”;
newmonth1<=oldmonth1+'1';else
newmonth0<=oldmonth0+'1';end if;end add_month;procedure sub_month(oldmonth0,oldmonth1:in std_logic_vector;
signal newmonth0:out std_logic_vector;signal newmonth1: out std_logic_vector)is begin
if oldmonth0=“0001”and oldmonth1=“0000”then
newmonth0<=“0010”;newmonth1<=“0001”;
elsif oldmonth0=“0000” and oldmonth1=“0001” then
newmonth0<=“1001”;newmonth1<= oldmonth1-'1';else newmonth0<=oldmonth0-'1';end if;if oldmonth0=“0000” and oldmonth1=“0000”then
newmonth0<=“0010”;newmonth1<=“0001”;
end if;
end sub_month;procedure sub_year(oldyear0,oldyear1:in std_logic_vector;signal newyear0: out std_logic_vector;signal newyear1: out std_logic_vector)is
begin if oldyear0=“0000”then
if oldyear1=“0000”then
newyear1<=“1001”;else newyear1<= oldyear1-'1';end if;newyear0<=“1001”;else newyear0<=oldyear0-'1';end if;end sub_year;procedure Feb_add_day(oldday0,oldday1:in std_logic_vector;
Ty0:in std_logic_vector(1 downto 0);
Ty1:in std_logic;
signal newday0: out std_logic_vector;
signal newday1: out std_logic_vector)is
begin
if oldday0=“1000”and oldday1=“0010”then
if((Ty1='0' and Ty0=“00”)or(ty1='1' and ty0=“10”))then
newday0<=oldday0 +'1';else newday0<=“0001”;newday1<=“0000”;end if;elsif oldday0=“1001” and oldday1=“0010”then
newday0<=“0001”;newday1<=“0000”;elsif oldday0=“1001” then
newday0<=“0000”;newday1<=oldday1+'1';else newday0<=oldday0+'1';end if;end Feb_add_day;
procedure Feb_sub_day(oldday0,oldday1:in std_logic_vector;
Ty0:in std_logic_vector(1 downto 0);
Ty1:in std_logic;
signal newday0: out std_logic_vector;
signal newday1: out std_logic_vector)is
begin
if(oldday0=“0000” or oldday0=“0001”)and oldday1=“0000”then
if((Ty1='0' and Ty0=“00”)or(ty1='1' and ty0=“10”))then
newday0<=“1001”;newday1<=“0010”;
else newday0<=“1000”;newday1<=“0010”;
end if;
elsif oldday0=“0000” and oldday1/=“0000”then
newday0<=“1001”;newday1<=oldday1-'1';else newday0<=oldday0-'1';end if;end Feb_sub_day;procedure oddmonth_add_day(oldday0,oldday1:in std_logic_vector;
signal newday0: out std_logic_vector;
signal newday1: out std_logic_vector)is
begin
if(oldday0=“0001” and oldday1=“0011”)then
newday0<=“0001”;newday1<=“0000”;
elsif oldday0=“1001”then
newday0<=“0000”;newday1<=oldday1+'1';
else newday0<= oldday0+'1';
end if;
end oddmonth_add_day;procedure oddmonth_sub_day(oldday0,oldday1:in std_logic_vector;
signal newday0: out std_logic_vector;
signal newday1: out std_logic_vector)is
begin
if(oldday0=“0001” or oldday0=“0000”)and oldday1=“0000” then
newday0<=“0001”;newday1<=“0011”;
elsif oldday0=“0000” and oldday1/=“0000” then
newday0<=“1001”;newday1<=oldday1-'1';
else newday0<= oldday0-'1';
end if;
end oddmonth_sub_day;procedure evenmonth_add_day(oldday0,oldday1:in std_logic_vector;
signal newday0: out std_logic_vector;
signal newday1: out std_logic_vector)is
begin
if oldday0=“0000” and oldday1=“0011” then newday0<=“0001”;
newday1<=“0000”;
elsif oldday0=“1001”then
newday0<=“0000”;
newday1<=oldday1+'1';
else newday0<=oldday0+'1';
end if;
end evenmonth_add_day;procedure evenmonth_sub_day(oldday0,oldday1:in std_logic_vector;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector)is begin
if(oldday0=“0000” or oldday0=“0001”)and oldday1=“0000”then
newday0<=“0000”;
newday1<=“0011”;elsif oldday0=“0000” and oldday1/=“0000”
then newday0<=“1001”;
newday1<=oldday1-'1';else
newday0<=oldday0-'1';
end if;end
evenmonth_sub_day;
procedure addsec_addmin(oldtime0,oldtime1:in std_logic_vector;
signal newtime0:out std_logic_vector;
signal newtime1:out std_logic_vector)is
begin
if
(oldtime0=“1001”)then
newtime0<=“0000”;
if(oldtime1=“0101”)then
newtime1<=“0000”;
else newtime1<=oldtime1+'1';
end if;
else newtime0<=oldtime0+'1';
end if;
end addsec_addmin;procedure subsec_submin(oldtime0,oldtime1:in std_logic_vector;
signal newtime0:out std_logic_vector;
signal newtime1:out std_logic_vector)is begin
if(oldtime0=“0000”)then
newtime0<=“1001”;
if(oldtime1=“0000”)then
newtime1<=“0101”;
else newtime1<=oldtime1-'1';
end if;
else newtime0<=oldtime0-'1';
end if;
end
subsec_submin;procedure addhour(oldhour0,oldhour1:in std_logic_vector;
signal newhour0:out std_logic_vector;
signal newhour1:out std_logic_vector)is begin
if(oldhour0=“1001”)then
newhour0<=“0000”;
newhour1<=oldhour1+'1';
else newhour0<=oldhour0+'1';
end if;
if oldhour0=“0011” and oldhour1=“0010”then
newhour0<=“0000”;newhour1<=“0000”;
end if;
end
addhour;procedure subhour(oldhour0,oldhour1:in std_logic_vector;
signal newhour0:out std_logic_vector;
signal newhour1:out std_logic_vector)is begin if oldhour0=“0000” then
newhour1<=oldhour1-'1';newhour0<=“1001”;
else newhour0<=oldhour0-'1';
end if;
if oldhour0=“0000” and oldhour1=“0000”then
newhour0<=“0011”;newhour1<=“0010”;
end if;
end
subhour;end pac;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity second_wave is
Port(f1000 : in std_logic;
second_wave1 : buffer std_logic);end second_wave;
architecture Behavioral of second_wave is signal cnt:std_logic_vector(8 downto 0);begin
process(f1000,cnt)
begin
if rising_edge(f1000)then
if(cnt=“111110011”)then
cnt<=“000000000”;second_wave1<=not second_wave1;
else cnt<=cnt+'1';
end if;
end if;
end process;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity settime is
Port(hour1,hour0,min1,min0,sec1,sec0 : in std_logic_vector(3 downto 0);
mytime,run : in std_logic;
result : out std_logic);end settime;
architecture Behavioral of settime is signal dhour1,dhour0,dmin1,dmin0,dsec1,dsec0:std_logic_vector(3 downto 0);begin p0:process(mytime)
begin
if mytime='1'then
dhour1<=hour1;
dhour0<=hour0;
dmin1<=min1;
dmin0<=min0;
dsec1<=sec1;
dsec0<=sec0;
end if;
end process p0;p1:process(run)
begin if run='1'then
if hour1=dhour1 and hour0=dhour0 and min1=dmin1 and min0=dmin0 and sec1=dsec1 and sec0 =dsec0 then
result<='1';
else result<='0';
end if;else result<='0';end if;
end process p1;end Behavioral;
第四篇：多功能数字钟课程设计
多功能数字钟
朱安烟
（安阳师范学院 物电学院, 河南 安阳 455002）
摘要：时钟相比具有更高的准确性和直观性
因此得到了更加广泛的使用。数字钟从原理上讲是一种典型的数字电路，其中
本设计采用六位LED
24小时计时方式根据数码管动态显示原理来进行显示。用晶振产生振荡脉加以分频得到所需的钟表秒脉冲,利用纯数字电路，实现数字电子时钟功能,时间重置功能。此次数字钟的理图设计，PCB图的制作主要是基于altium designer软件，利用proteus7.7软件进行仿真，最终本设计实现24小时的时钟计时、时间重置功能。
关键词：LED数码管
时序电路
逻辑电路
时钟
校时引言
仅向。方案论证：
2.1方案一
由于是数字钟的设计，可以用单片机AT89C51来实现计数功能，相对于纯数字电路来讲它具有功耗低、体积小、使用方便等优点。但在大二下半学期初期，对单片机方面的内容知识还不够完善，加上用单片机为核心来做数字钟还需做编程，对自身来说又是一难点。不过此法可以待以后，学习知识完善后再考虑。
2.2 方案二
继而考虑到用原先学过的纯数字电路来做，以74Ls160来做为计数的芯片，用六片分别实现 数字钟的小时、分、秒、的计数，并用晶振加以分频产生数字钟所需的秒脉冲。
从以上两种方案，很容易看出，采用方案二，用此法做即可以复习回顾早期学习的数电模电知识，又避免了单片机知识不足的问题，故用此法。结果与讨论
3.1.1数字钟主要计数芯片为74ls160其引脚图如下：
这种同步可预置十进计数器是由四个D型触发器和若干个门电路构成，内部有超前进位，具有计数、置数、禁止、直接（异步）清零等功能。对所有触发器同时加上时钟，使得当计数使能输入和内部门发出指令时输出变化彼此协调一致而实现同步工作。这种工作方式消除了非同步（脉冲时钟）计数器中常有的输出计数尖峰。缓冲时钟输入将在时钟输入上升沿触发四个触发器。这种计数器是可全编程的，即输出可预置到任何电平。当预置是同步时，在置数输入上将建立一低电平，禁止计数，并在下一个时钟之后不管使能输入是何电平，输出都与建立数据一致。清除是异步的（直接清零），不管时钟输入、置数输入、使能输入为何电平，清除输入端的低电平把所有四个触发器的输出直接置为低电平。超前进位电路无须另加门，即可级联出n位同步应用的计数器。它是借助于两个计数使能输入和一个动态进位输出来实现的。两个计数使能输入（ENP和ENT）计数时必须是高电平，且输入ENT必须正反馈，以便使能动态进位输出。因而被使能的动态进位输出将产生一个高电平输出脉冲，其宽度近似等于QA输出高电平。此高电平溢出进位脉冲可用来使能其后的各个串联级。使能ENP和ENT输入的跳变不受时钟输入的影响。电路有全独立的时钟电路。改变工作模式的控制输入（使能ENP、ENT或清零）纵使发生变化，直到时钟发生为止，都没有什么影响。计数器的功能（不管使能、不使能、置数或计数）完全由稳态建立时间和保持时间所要求的条件来决定。
管脚说明： CLR:清零复位端
当输入为低电平时有效
CLK：时钟信号接收端
A~D:读入
QA~QD:输出
ENT、ENP置一时芯片正常工作
LOAD:置数端
RCO：信号输出端
GND：接地
Vcc：接高
工作方式：
3.1.2 7段LED数码管
3.1.3 32.768KHZ晶振
32.768KHZ是一个标准的频率，晶振频率的应用主要有以下几个方面的参数：尺寸、负载电容、频率偏差、应用范围。按尺寸外形来分主要分为插件和贴片的；插件的主要有2*
6、3*
8、49s 等，贴片的就有很多种了，跟据各公司的设计可的型号有很多，例如：日本KDS晶振就有49SMD、DST310S、SM—14J、DST520、DST410S等。
3.1.4 CD4060分频器
CD4060由一振荡器和14级二进制串行计数器位组成，振荡器的结构可以是RC或晶振电路，CR为高电平时，计数器清零且振荡器使用无效。所有的计数器位均为主从触发器。在CP1(和CP0)的下降沿计数器以二进制进行计数。在时钟脉冲线上使用斯密特触发器对时钟上升和下降时间无限制 引脚功能：
/CP1：时钟输入端
/CP0：时钟输出端
/CP0：反相时钟输出端
Q4~Q10，Q12~Q14：计数器输出端
/Q14：第14级计数器反相输出端
VDD：电源正
VSS：电源负
CR：清零端 3.1.5 74ls48
功能介绍：
74LS48除了有实现7段显示译码器基本功能的输入（DCBA）和输出（Ya～Yg）端外，7448还引入了灯测试输入端（LT）和动态灭零输入端（RBI），以及既有输入功能又有输出功能的消隐输入/动态灭零输出（BI/RBO）端。
由7448真值表可获知7448所具有的逻辑功能：
（1）7段译码功能（LT=1，RBI=1）
在灯测试输入端（LT）和动态灭零输入端（RBI）都接无效电平时，输入DCBA经7448译码，输出高电平有效的7段字符显示器的驱动信号，显示相应字符。除DCBA = 0000外，RBI也可以接低电平，见表1中1～16行。
（2）消隐功能（BI=0）
此时BI/RBO端作为输入端，该端输入低电平信号时，表1倒数第3行，无论LT 和RBI输入什么电平信号，不管输入DCBA为什么状态，输出全为“0”，7段显示器熄灭。该功能主要用于多显示器的动态显示。
（3）灯测试功能（LT = 0）
此时BI/RBO端作为输出端，端输入低电平信号时，表1最后一行，与 及DCBA输入无关，输出全为“1”，显示器7个字段都点亮。该功能用于7段显示器测试，判别是否有损坏的字段。
（4）动态灭零功能（LT=1，RBI=1）
此时BI/RBO端也作为输出端，LT 端输入高电平信号，RBI 端输入低电平信号，若此时DCBA = 0000，表1倒数第2行，输出全为“0”，显示器熄灭，不显示这个零。DCBA≠0，则对显示无影响。该功能主要用于多个7段显示器同时显示时熄灭高位的零。
3.2 原理设计
整体电路设计方案：
3.2.1 振荡电路设计
振荡电路由振荡器产生的脉冲，振荡器是数字钟的核心。振荡器的稳定度及频率的精度决定了数字钟的精确程度，次处有555定时器和晶振两种产生秒脉冲的方法：555振荡器做振荡源一般用于精确度要求不高的场合，由门电路组成的多谐振荡器的振荡周期不仅与时间常数RC有关，而且还取决于门电路的阈值电压VTH，由于VTH容易受到温度、电源电压及干扰的影响，因此频率稳定性较差，只能用于对频率稳定性要求不高的场合。考虑到振荡频率的精确度与稳定性固采用晶振做为振荡源来实现振荡电路，得时钟脉冲更稳定，时间走的更准37.268KHz晶振 通过cd4060分频器进行十四分频得到0.5s的脉冲信号，再进行一个SN74LS74进行二分频得到所需的秒脉冲信号：
3.2.2 校时电路设计
根据电路设计所知需要在分处和小时处需要校时，分别在分和时个位向十位进位处各加一开关，另一端接地并且在与地之间接100pf电容为防止按键抖动。
电路设计如下：
当开关处于自然位置时分十位clk端所接为高电平，当开关按下时则引入一低电平实其clk端有一个下降沿脉冲接入，使其产生了校时功能。
3.2.3显示电路设计
显示电路是用74ls48驱动七段共阴数码管来作为时钟显示器。
电路设计如下：
3.2.4 计时电路设计
数字钟的秒和分位都是从0到60循环计数的，所以可以用用异步清零法设计60进制计数器作为秒和分的计数器。用异步置数法设计小时所用的24进制计数器。秒、分位设计电路如下：
3.3 程序调试过程
在板子焊接好以后通上5V电源发现六Led灯只有三个能完整亮出来，其余的都不亮或是亮的不全，而且秒位不走，校时按键不管用。问题很多。
开始调试：
1、首先调试的是秒位为何不走，先测晶振石否起振，测量后发现晶振正常起振，然后从74ls160的clk端用示波器测试一下没有脉冲信号输入，则找74ls74的输出口也无脉冲，以次往前推，最后测量出从74ls74输入端有正确的脉冲输入，输出端却无脉冲输出。观察后没有连接错误，故用万用表测vcc.end端都有正确的电平接入，再测量两点间是否有漏焊现象，最后测出一处漏焊点使D端与Q端没有接通。重新焊接后秒位正常计时。
2、秒位正常计时，但向秒的十位进位时总是显示从8到19，查阅资料可知，在第一个160芯片到第二个160芯片中缺一个非门，充当延时作用，使个位计数到9再来一个脉冲下计数时再向前进位。加上非门进位正常了。
3、秒位向分位进位正常，但校时按键不能用，且分位向十分位不能进位，通过观察焊接对比原理图与pcb图后发现，开关接地的一端弄反了，应是开关与接电容端相侧对着的端接地。这个错误导致开关不能用，亦使分的十位端的74ls160芯片clk段一直接了地，故不能使其正常进位。修改过后则可以正常进位，且两开关都能用了。
4、显示小时位的第一个数码管一直不亮，通过测量发现led数码管没有烧坏，能正常工作，通过对比PCB图观察没有焊接错误，用万用表测量则发现驱动次led的74ls48管没有正常接地，连接跳线处有一虚焊，重新焊接后恢复正常。
5、但分向小时不能进位，由示波器观察发现74ls160芯片clk端无脉冲输入，但十分位有脉冲输出，且导线也导通了，就观察原理图发现原理图一处错误，分向时进位时是分满60向前进一个脉冲，故分的TC端不用再接到时的CLK端了。找到错误后用镊子将板上的铜线划段，则正常进位了。
6、小时进位正常但显示的不是24进制，显示的是44进制，则推测可能是跳线连接错误，将显示小时的十位 74ls160芯片接B端连接成接C端了，故使其显示44进制，通过观察、对比pcb图，最后发现果然如此。修改过后小时为正常24进制了。
7、最后一个数码管有三段老是不亮，观察连接没有错误，测量焊接也正常，最后用万用表测量发现芯片没有问题，那三段不亮的数码管烧了。
8、调试好后在后来的观察中发现从秒向分进位时有时一下进两位，自己找不出来原因。问过老师后，老师说是由于防抖电容所致。尝试着将电容先划断试了一下就没有那种情况了。但此时校时开关由于抖动缘故，按一下有时跳3、4个位，校时不稳定了。结论
此数字钟相对于机械钟来说有低功耗，高精度，数字化显示和不易损坏等特点。符合人们日常家居及办公对钟表的要求，可以作为家居、办公等用表。
参考文献
[1] 佘新平数学电子技术基础 华中科技大学出版社 2009年
[2] 许树玲 丁电宽 王晋 电子技术及实验 内蒙古大学出版社2005年
[3] 佘新平数字电路设计·仿真·测试 华中大学出版社 2010年
附图: 电路原理图:
第五篇：多功能数字钟课程设计报告
课题名称 姓名 学号 院、系、部 专业 指导教师
电子技术课程设计报告书
2016年6月12日
一、设计任务及要求：
用中小规模集成芯片设计并制作多功能数字钟，具体要求如下：
1、准确及时，以数字形式显示时（00～23）、分（00～59）、秒（00～59）的时间。
2、具有校时功能。指导教师签名：
2016
二、指导教师评语：
指导教师签名：
2016
三、成绩
指导教师签名：
2016年6月年6月年6月日
日
日
多功能数字钟课程设计报告 设计目的
一、设计原理与技术方法：
包括：电路工作原理分析与原理图、元器件选择与参数计算、电路调试方法与结果说明； 软件设计说明书与流程图、软件源程序代码、软件调试方法与运行结果说明。
1、电路工作原理分析与原理图
数字钟实际上是一个对标准频率（1Hz）进行计数的计数电路。由于标准的1Hz 时间信号必须做到准确稳定，所以通常使用输出频率稳定的石英晶体振荡器电路构成数字钟的振源。又由于计数的起始时间不可能与标准时间（如北京时间）一致，故需要在电路上加一个校时电路。因此一个具有计时、校时、报时、显示等基本功能的数字钟主要由振荡器、分频器、计数器、译码器、显示器、校时电路、报时电路等七部分组成。石英晶体振荡器产生的信号经过分频器得到秒脉冲后，秒脉冲送入计数器计数，计数结果通过“时”、“分”、“秒”译码器译码，并通过显示器显示时间。由以上分析可得到原理框图如下图
图1 实验原理框图
2、元器件选择与参数计算
（1）晶体振荡电路：产生秒脉冲既可以采用555脉冲发生电路也可以采用晶振脉冲发生电路。若由集成电路定时器555与RC组成的多谐振荡器作为时间标准信号源，可使555与RC组成多谐振荡器，产生频率 f=1kHz的方波信号，再通过分频则可得到秒脉冲信号。晶体振荡器电路则可以给数字钟提供一个频率稳定准确的32768Hz的方波信号，可保证数字钟的走时准确及稳定。相比二者的稳定性，晶振电路比555电路能够产生更加稳定的脉冲，数字电路中的时钟是由振荡器产生的，振荡器是数字钟的核心。振荡器的稳定度及频率的精度决定了数字钟计时的准确程度，所以最后决定采用晶振脉冲发生电路。石英晶体振荡器的特点是振荡频率准确、电路结构简单、频率易调整，它是电子钟的核心，用它产生标准频率信号，再由分频器分成秒时间脉冲。
所以秒脉冲晶体振荡选用32768Hz的晶振，该元件专为数字钟电路而设计，其频率较低，有利于减少分频器级数。从有关手册中，可查得C1、C2均为20pF。当要求频率准确度和稳定度更高时，还可接入校正电容并采取温度补偿措施。由于CMOS电路的输入阻抗极高，因此反馈电阻R1可选为20MΩ。
（2）分频器电路：分频器电路将32768Hz的高频方波信号经32768（152）次分频后得到1Hz的方波信号供秒计数器进行计数。分频器实际上也就是计数器。该电路可通过CD4060与双D触发器74LS74共同实现。
（3）时间计数器电路：时间计数电路由秒个位和秒十位计数器、分个位和分十位计数器及时个位和时十位计数器电路构成，其中秒个位和秒十位计数器、分个位和分十位计数器为60进制计数器，而根据设计要求，时个位和时十位计数器为24进制计数器。计数器可以使用十进制的74LS160。
（4）译码驱动电路：译码驱动电路将计数器输出的8421BCD码转换为数码管需要的逻辑状态，并且为保证数码管正常工作提供足够的工作电流。译码器可以使用CD4511。
（5）校时电路：可以通过基本的门器件、电阻与开关实现。由设计的电路图可选择与非门74LS00。（6）整点报时电路：一般时钟都应具备整点报时电路功能,即在时间出现整点前数秒内,数字钟会自动报时,以示提醒.其作用方式是发出连续的或有节奏的音频声波。
3、电路调试方法与结果说明（1）电路调试方法 ①数码管的调试：可以用万用表的负极接数码管的3或8脚，正极依次接数码管剩余的管脚所接电阻的另一端，并将万用表调至测发光二极管档位，从而测试数码管的显示是否正确。②“时”“分”“秒”电路的调试：将“时”“分”“秒”电路连接完成后，可以用函数信号发生器产生的1Hz方波信号分别作为“时”、“分”、“秒”的个位74LS160的计数脉冲，从而测试“时”是否为24进制，“分”和“秒”是否为60进制。③校时电路的调试：先将电路外接用函数信号发生器产生的2Hz方波信号，再分别通过校时、校分电路开关的断开、闭合以及开关闭合后电路的工作情况判断电路的校时、校分功能是否正确。
④秒脉冲产生电路的调试：将电路产生的秒时间脉冲接入示波器，观察并计算电路是否产生1Hz方波信号。（2）结果说明
①数码管的调试：当正极依次接1、2、4、5、7、9、10管脚时，数码管依次是G、F、A、B、C、D、E亮。②“时”“分”“秒”电路的调试：“时”为24进制（从“00”到“23”），“分”和“秒”都为60进制（从“00”到“59”）。
③校时电路的调试：开关断开时电路处于正常工作状态，开关闭合时电路处于校时、校分状态。
④秒脉冲产生电路的调试：电路产生1Hz方波信号。
4、软件设计说明书与流程图（1）秒脉冲产生电路
晶体振荡器是构成数字式时钟的核心，它保证了时钟的走时准确及稳定。由于晶体具有较高的频率稳定性及准确性，从而保证了输出频率的稳定和准确。晶体XTAL的频率选为32768HZ。该元件专为数字钟电路而设计，其频率较低，有利于减少分频器级数。从有关手册中，可查得C1、C2均为20pF。当要求频率准确度和稳定度更高时，还可接入校正电容并采取温度补偿措施。由于CMOS电路的输入阻抗极高，因此反馈电阻R1可选为22MΩ。较高的反馈电阻有利于提高振荡频率的稳定性。通常，数字钟的晶体振荡器输出频率较高，为了得到1Hz的秒信号输入，需要对振荡器的输出信号进行分频。通常实现分频器的电路是计数器电路，一般采用多级２进制计数器来实现。
本实验中采用CD4060来构成分频电路。管脚图见图2。CD4060在数字集成电路中可实现的分频次数最高，而且CD4060还包含振荡电路所需的非门，使用更为方便。CD4060计数为14级2进制计数器，可以将32768Hz的信号分频为2Hz，再经过74LS74即可获得1Hz的方波信号。原理电路图如图3所示，图4为仿真电路图。
图2 D4060管脚图
图3 CD4060秒脉冲振荡发生器
图 4 产生1Hz时间脉冲的电路图
（2）时间计数器电路 ①“秒”“分”电路
根据题目要求，“秒”和“分”都是60进制的，而且是从“00”到“59”，可以使用十进制的74LS160来实现这个功能。首先将两片74LS160通过串行进位方式接成百进制计数器，即分别将“秒”和“分”个位的进位输出信号经非门作为“秒”和“分”十位的计数输入脉冲。当计数器从全0状态开始计数，计入59个脉冲时，经与非门译码产生低电平信号立刻将两片74LS160同时置零，于是便得到了60进制的计数器。74160的逻辑功能示意图、引脚图及功能表如下所示。
图5 a)74160逻辑功能示意图
b)74160引脚图
图6 74160逻辑功能表 ②“时”电路 根据题目要求，“时”是24进制的，而且是从“00”到“23”，可以使用十进制的74LS160来实现这个功能。首先将两片74LS160通过串行进位方式接成百进制计数器，当计数器从全0状态开始计数，计入23个脉冲时，经与非门译码产生低电平信号立刻将两片74LS160同时置零，于是便得到了24进制的计数器。（3）译码驱动电路
计数器实现了对时间的累计以8421BCD码形式输出，选用显示译码电路将计数器的输出数码转换为数码显示器件所需要的输出逻辑和一定的电流，选用CD4511作为显示译码电路，选用LED数码管作为显示单元电路。由于CD4511是输出高电平有效，所以选用七段共阴极LED数码管。若将“秒”、“分”、“时”计数器的每位输出分别接到相应七段译码器的输入端，便可进行不同数字的显示。“秒”用数码管显示如图7所示。
图7 “秒”的译码及驱动显示电路图（4）校时电路
数字种启动后,每当数字钟显示与实际时间不符合,需要根据标准时间进行校时。通常，校正时间的方法是：首先截断正常的计数通路，然后再进行人工触发计数或将频率较高的方波信号加到需要校正的计数单元的输入端，校正好后，再转入正常计时状态即可。校“秒”时，采用等待校时。校“分”、“时”的原理比较简单，采用加速校时。对校时电路的要求是 : 1．在小时校正时不影响分和秒的正常计数。2．在分校正时不影响秒和小时的正常计数。当开关断开时，因为校正信号和0相与的输出为0，而开关的另一端接高电平，正常输入信号可以顺利通过与或门，故校时电路处于正常计时状态；当开关闭合时，情况正好与上述相反，这时校时电路处于校时状态。与非门可选74LS00，非门则可用与非门2个输入端并接来代替从而节省芯片。校时电路图见图8。
校时电路图（5）整点报时电路
一般时钟都应具备整点报时电路功能，即在时间出现整点前数秒内，数字钟会自动报时，以示提醒。其作用方式是发出连续的或有节奏的音频声波。当时间在59分50秒到59分59秒期间时，分十位、分个位和秒十位均保持不变，分别为5、9和5，因此可将分计数器十位的QC和QＡ、个位的QＤ和QＡ及秒计数器十位的QＣ 和QＡ相与。电路在整点前6秒钟内开始整点报时，即当时间在59分54秒到59分59秒期间时，报时电路产生报时控制信号，控制小喇叭产生低音；当时间为00分00秒时，报时电路产生报时控制信号，控制小喇叭产生高音。
5、软件调试方法与运行结果说明（1）软件调试方法
由于仿真时晶振不能正常工作，所以通过外接1KHz方波信号来调试电路。“时”“分”“秒”电路的调试：“时”为24进制（从“00”到“23”），“分”和“秒”都为60进制（从“00”到“59”）。校时电路的调试：可以通过校时、校分电路的开关来校对时间，并判断电路的“时”“分”“秒”的进制是否正确。开关断开时电路处于正常工作状态，开关闭合时电路处于校时、校分状态。（2）运行结果说明
数码管的各部分可以正确显示，电路的“时”为24进制（从“00”到“23”），“分”和“秒”都为60进制（从“00”到“59”）。开关断开时电路处于正常工作状态，开关闭合时电路处于校时、校分状态，通过控制开关及输入信号可以达到校时功能。
三、设计体会与建议 1.设计体会
我觉得此次的数字钟设计实验，电路原理相对来比较简单，但电路图比较复杂，所用芯片比较多，相应的连线也多，这就给焊接电路增加了较大的难度。不过通过此次实验，使我更进一步地熟悉了芯片的结构，掌握了实验中所用各芯片的工作原理和其具体的使用方法，同时还接触到了一些新认识的芯片，增长了见识。这次课程设计是一次难得的锻炼机会，让我们能够充分运用所学过的理论知识和自己动手实际操作的能力，另外还让我们学习查找资料的方法，以及自己设计电路、焊接电路、分析解决电路存在的问题的能力。这对于我来说是很好的提高，填补了平日理论学习后实践方面的空白。参考文献
[1] 阎石.数字电子技术基础[M].北京：高等教育出版社，2001年
[2] 杨素行.模拟电子技术基础简明教程[M].北京：高等教育出版社，2005年 [3]康华光.电子技术基础[M].北京：高等教育出版社，1999年 [4]彭华林等编.数字电子技术[M].长沙：湖南大学出版社，2004年 [5]金唯香等编.电子测试技术[M].长沙：湖南大学出版社，2004年
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