第一篇：用状态机实现的EDA多功能数字钟课程设计VHDL代码
设计并实现具有一定功能的数字钟
1、该数字钟可以实现3个功能：计时功能、整点报时功能和重置时间功能，因此有3个功能：计时、重置时间、复位。
2、对所有设计的小系统能够正确分析；
3、基于VHDL语言描述系统的功能；
4、在quartus 2环境中编译通过；
5、仿真通过并得到正确的波形；
6、给出相应的设计报告。
其中计时模块有4部分构成：秒计时器（second）、分计时器(minute)、时计时器(hour)、日计时器(date)、月计时器（mouth）、年计时器（year）
1）秒计时器（second）是由一个60进制的计数器构成的，具有清0、置数和计数功能。其中reset为清0信号，当reset为0时，秒计时器清0；set 为置数信号，当set为0时，秒计时器置数，置s1的值。clk为驱动秒计时器的时钟，sec为秒计时器的输出，ensec为秒计时器的进位信号，作为下一级的时钟输入信号。
2）分计时器（minute）是由一个60进制的计数器构成的，具有清0、置数和计数功能。其中reset为清0信号，当reset为0时，分计时器清0；set 为置数信号，当set为0时，分计时器置数，置m1的值。clkm为驱动分计时器工作的时钟，与ensec相连接；min为分计时器的输出；enmin为分计时器的进位信号，作为下一级的时钟输入信号。
3）时计时器（hour）是由一个24进制的计数器构成的，具有清0、置数和计数功能。其中reset为清0信号，当reset为0时，时计时器清0；set 为置数信号，当set为0时，时计时器置数，置h1的值。clkh为驱动时计时器工作的时钟，与enmin相连接；hour为时计时器的输出；enhour为时计时器的进位信号，作为下一级的时钟输入信号。
4）日计时器（date1）是由一个60进制的计数器构成的，具有清0、置数和计数功能。其中reset为清0信号，当reset为0时，星期计时器清0；set 为置数信号，当set为0时，星期计时器置数，置d1的值。clkd为驱动星期计时器工作的时钟，与enhour相连接；date为日计时器的输出，endate为分计时器的进位信号，作为下一级的时钟输入信号，由于月份的天数存在天数不同，闰年2月的天数为28天等情况，还设计了一个润年判别器，准确显示时间。
5）月计时器（mouth）是由一个60进制的计数器构成的，具有清0、置数和计数功能。其中reset为清0信号，当reset为0时，星期计时器清0；set 为置数信号，当set为0时，星期计时器置数，置mou1的值，clkmou为驱动星期计时器工作的时钟，与enday相连接；mou为日计时器的输出，enmou为分计时器的进位信号，作为下一级的时钟输入信号。6）计时器（year）是由一个60进制的计数器构成的，具有清0、置数和计数功能。其中reset为清0信号，当reset为0时，星期计时器清0；set 为置数信号，当set为0时，星期计时器置数，置y1的值，clky为驱动星期计时器工作的时钟，与enmou相连接；year为日计时器的输出。VHDL程序
1、屏幕切换模块
运用状态机进行屏幕切换，分别显示年月日，以及时分秒 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity mux3 is
Port(clk,Reset,sel : in std_logic;
int1,int2,int3,int4,int5,int6,int7,int8,int9,int10,int11,int12:IN STD_LOGIC_VECTOR(3 DOWNTO 0);--rst must
a1,a2,a3,a4,a5,a6: out std_logic_vector(3 downto 0));end mux3;
architecture Behavioral of mux3 is
TYPE states IS(st0, st1, st2, st3, st4, st5, st6, st7);
SIGNAL STX: states;
begin
COM1 : PROCESS(STX,int1,int2,int3,int4,int5,int6,int7,int8,int9,int10,int11,int12)
BEGIN--决定转换状态的进程
CASE STX IS
WHEN st0 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;
WHEN st1 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;
WHEN st2 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;
WHEN st3 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;
WHEN st4 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;
WHEN st5 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;
WHEN st6 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;
WHEN st7 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;
WHEN OTHERS => NULL;
END CASE;
END PROCESS COM1;REG: PROCESS(clk,Reset,sel)
--主控时序进程
BEGIN
IF Reset = '1' THEN
STX<= st0;
--异步复位
ELSIF clk='1' AND clk'EVENT THEN
if sel='1' then
CASE STX IS
WHEN st0=>STX<=st1;
WHEN st1=>STX<=st2;
WHEN st2=>STX<=st3;
WHEN st3=>STX<=st4;
WHEN st4=>STX<=st5;
WHEN st5=>STX<=st6;
WHEN st6=>STX<=st7;
WHEN st7=>STX<=st0;
END CASE;
END IF;
END if;END PROCESS;
2、显示切换程序 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity mux1 is
Port(clk,ina,inb,sel,Reset : in std_logic;
result : out std_logic);end mux1;
architecture Behavioral of mux1 is
TYPE state IS(st0,st1,st2,st3,st4,st5,st6,st7);
SIGNAL STX:state;begin REG1: PROCESS(ina,inb,STX)
BEGIN
CASE STX IS
WHEN st0=>result<=ina;
WHEN st1=>result<=ina;
WHEN st2=>result<=inb;
WHEN st3=>result<=inb;
WHEN st4=>result<=inb;
WHEN st5=>result<=inb;
WHEN st6=>result<=inb;
WHEN st7=>result<=inb;
END CASE;
END PROCESS;REG2:PROCESS(clk,sel,Reset)BEGIN IF(Reset='1')THEN
STX<=st0;ELSIF(clk'EVENT AND clk='1')THEN
if sel='1' then CASE STX IS WHEN st0=>STX<=st1;WHEN st1=>STX<=st2;WHEN st2=>STX<=st3;WHEN st3=>STX<=st4;WHEN st4=>STX<=st5;WHEN st5=>STX<=st6;WHEN st6=>STX<=st7;WHEN st7=>STX<=st0;
END CASE;END IF;end if;END PROCESS REG2;
end Behavioral;
3、置数操作模块
运用状态机，进行置数操作 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity mux is
Port(clk,ina,inb,sel,Reset : in std_logic;
r1,r2,r3,r4,r5,r6 : out std_logic);end mux;
architecture Behavioral of mux is TYPE state IS(st0,st1,st2,st3,st4,st5,st6,st7);
SIGNAL STX:state;begin PROCESS(ina,inb,STX)BEGIN CASE STX IS WHEN st0=>r1<=ina;r2<='0';r3<='0';r4<='0';r5<='0';r6<='0';WHEN st1=>r1<=ina;r2<='0';r3<='0';r4<='0';r5<='0';r6<='0';WHEN st2=>r1<='0';r2<='0';r3<='0';r4<='0';r5<='0';r6<=inb;WHEN st3=>r1<='0';r2<='0';r3<='0';r4<='0';r5<=inb;r6<='0';WHEN st4=>r1<='0';r2<='0';r3<='0';r4<=inb;r5<='0';r6<='0';WHEN st5=>r1<='0';r2<='0';r3<=inb;r4<='0';r5<='0';r6<='0';WHEN st6=>r1<='0';r2<=inb;r3<='0';r4<='0';r5<='0';r6<='0';WHEN st7=>r1<=inb;r2<='0';r3<='0';r4<='0';r5<='0';r6<='0';END CASE;END PROCESS;PROCESS(clk,sel,Reset)BEGIN IF(Reset='1')THEN STX<=st0;ELSIF(clk'EVENT AND clk='1')THEN if sel='1' then CASE STX IS WHEN st0=>STX<=st1;WHEN st1=>STX<=st2;WHEN st2=>STX<=st3;WHEN st3=>STX<=st4;WHEN st4=>STX<=st5;WHEN st5=>STX<=st6;WHEN st6=>STX<=st7;WHEN st7=>STX<=st0;
END CASE;END IF;end if;END PROCESS;end Behavioral;end Behavioral;
4、秒显示模块 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity secute1 is
Port(clkm,set,reset : in std_logic;
sec2,sec1 : inout std_logic_vector(3 downto 0);
ensec : out std_logic);end secute1;
architecture Behavioral of secute1 is
begin
Process(clkm,reset,set)
Begin
If reset='1' then sec2<=“0000”;sec1<=“0000”;
Elsif set='1' then sec2<=“0101”;sec1<=“1000”;
Elsif(clkm'event and clkm='1')then
if sec2=“0101” AND sec1=“1001” then sec2<=“0000”;sec1<=“0000”;ensec<='1';
elsif sec1=“1001” then sec2<=sec2+'1';sec1<=“0000”;ensec<='0';
else sec1<=sec1+'1';ensec<='0';
end if;end if;End process;end Behavioral;
5、分显示模块 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity minute1 is
Port(clkm,set,reset : in std_logic;
min2,min1 : inout std_logic_vector(3 downto 0);
enmin : out std_logic);end minute1;
architecture Behavioral of minute1 is
begin
Process(clkm,reset,set)
Begin
If reset='1' then min2<=“0000”;min1<=“0000”;
Elsif set='1' then min2<=“0101”;min1<=“1000”;
Elsif(clkm'event and clkm='1')then
if min2=“0101” AND min1=“1001” then min2<=“0000”;min1<=“0000”;enmin<='1';
elsif min1=“1001” then min2<=min2+'1';min1<=“0000”;enmin<='0';
else min1<=min1+'1';enmin<='0';
end if;end if;End process;end Behavioral;
6、小时显示模块 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity hour1 is
Port(clkh,set,reset: in std_logic;
hor2,hor1 : inout std_logic_vector(3 downto 0);
enhour : out std_logic);end hour1;
architecture Behavioral of hour1 is
begin Process(clkh,reset,set)
Begin
If reset='1' then hor2<=“0000”;hor1<=“0000”;
Elsif set='1' then hor2<=“0010”;hor1<=“0011”;
Elsif(clkh'event and clkh='1')then
if hor2=“0010” AND hor1=“0011” then hor2<=“0000”;hor1<=“0000”;enhour<='1';
elsif hor1=“1001” then hor2<=hor2+'1';hor1<=“0000”;enhour<='0';
else hor1<=hor1+'1';enhour<='0';
end if;
end if;End process;end Behavioral;
7、日显示模块（已加入闰年判断功能）library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity date1 is
Port(clkd,set : in std_logic;
dat2,dat1 : inout std_logic_vector(3 downto 0);
endate : out std_logic);end date1;
architecture Behavioral of date1 is
begin
Process(clkd,set)
Begin
if set='1' then dat2<=“0010”;dat1<=“1000”;
Elsif(clkd'event and clkd='1')then
if dat2=“0011” AND dat1=“0000” then dat2<=“0000”;dat1<=“0001”;endate<='1';elsif dat1=“1001” then dat2<=dat2+'1';dat1<=“0000”;endate<='0';
else dat1<=dat1+'1';endate<='0';
end if;end if;End process;end Behavioral;
8、月显示模块 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity month1 is
Port(clkn,set: in std_logic;
mon2,mon1 : inout std_logic_vector(3 downto 0);
enmon : out std_logic);end month1;
architecture Behavioral of month1 is
begin
Process(clkn,set)
Begin
if set='1' then mon2<=“0000”;mon1<=“0110”;
Elsif(clkn'event and clkn='1')then
if mon2=“0001” AND mon1=“0010” then mon2<=“0000”;mon1<=“0001”;enmon<='1';
elsif mon1=“1001” then mon2<=mon2+'1';mon1<=“0000”;enmon<='0';
else mon1<=mon1+'1';enmon<='0';
end if;end if;End process;
9、年显示模块 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity yearth1 is
Port(clkn,set: in std_logic;
year2,year1 : inout std_logic_vector(3 downto 0);
enyear : out std_logic);end yearth1;
architecture Behavioral of yearth1 is
begin
Process(clkn,set)
Begin
if set='1' then year2<=“0001”;year1<=“0001”;
Elsif(clkn'event and clkn='1')then
if year2=“1001” AND year1=“1001” then year2<=“0000”;year1<=“0001”;
elsif year1=“1001” then year2<=year2+'1';year1<=“0000”;enyear<='0';
else year1<=year1+'1';enyear<='0';
end if;end if;
end Behavioral;
第二篇：EDA课程设计——多功能数字钟
哈尔滨工业大学(威海)电子学课程设计报告
带有整点报时的数字钟设计与制作
姓名: 蒋栋栋 班级: 0802503 学号: 080250331 指导教师:
井岩
目录
一、课程设计的性质、目的和任务„„„„„„„„„„„„3
二、课程设计基本要求„„„„„„„„„„„„„„„„„3
三、设计课题要求„„„„„„„„„„„„„„„„„„„3
四、课程设计所需要仪器„„„„„„„„„„„„„„„„4
五、设计步骤„„„„„„„„„„„„„„„„„„„„„4
1、整体设计框图„„„„„„„„„„„„„„„„„„„4
2、各个模块的设计与仿真„„„„„„„„„„„„„„„4
2.1分频模块„„„„„„„„„„„„„„„„„„„„„„„4
2.2计数器模块„„„„„„„„„„„„„„„„„„„„„„6
2.3控制模块„„„„„„„„„„„„„„„„„„„„„„10
2.4数码管分配„„„„„„„„„„„„„„„„„„„„„13
2.5显示模块„„„„„„„„„„„„„„„„„„„„„„14
2.6报时模块„„„„„„„„„„„„„„„„„„„„„„16
六、调试中遇到的问题及解决的方法„„„„„„„„„„„18
七、心得体会„„„„„„„„„„„„„„„„„„„„„18
一、课程设计的性质、目的和任务
创新精神和实践能力二者之中，实践能力是基础和根本。这是由于创新基于实践、源于实践，实践出真知，实践检验真理。实践活动是创新的源泉，也是人才成长的必由之路。
通过课程设计的锻炼，要求学生掌握电路的一般设计方法，具备初步的独立设计能力，提高综合运用所学的理论知识独立分析和解决问题的能力，培养学生的创新精神。
二、课程设计基本要求
掌握现代大规模集成数字逻辑电路的应用设计方法，进一步掌握电子仪器的正确使用方法，以及掌握利用计算机进行电子设计自动化(EDA)的基本方法。
三、设计课题要求
（1）构造一个24小时制的数字钟。要求能显示时、分、秒。（2）要求时、分、秒能各自独立的进行调整。
（3）能利用喇叭作整点报时。从59分50秒时开始报时，每隔一秒报时一秒，到达00分00秒时，整点报时。整点报时声的频率应与其它的报时声频有明显区别。
#设计提示（仅供参考）：（1）对频率输入的考虑
数字钟内所需的时钟频率有：基准时钟应为周期一秒的标准信号。报时频率可选用1KHz和2KHz左右(两种频率相差八度音，即频率相差一倍)。另外，为防止按键反跳、抖动，微动开关输入应采用寄存器输入形式，其时钟应为几十赫兹。
（2）计时部分计数器设计的考虑 分、秒计数器均为模60计数器。
小时计数为模24计数器，同理可建一个24进制计数器的模块。（3）校时设计的考虑
数字钟校准有3个控制键：时校准、分校准和秒校准。
微动开关不工作，计数器正常工作。按下微动开关后，计数器以8Hz频率连续计数(若只按一下，则计数器增加一位)，可调用元件库中的逻辑门建一个控制按键的模块，即建立开关去抖动电路(见书70页)。
（4）报时设计的考虑
可以将高频时钟分频得到约2KHz和1KHz的音频，作为数字钟的报时频率。当电子钟显示XX：59：50时，数字钟开始报时“DO“，持续一秒，而且每隔一秒报一下，直至显示XX：00：00时报“DI”，持续一秒后停止。最后输出至喇叭。应调用元件库中的逻辑门建一个控制报时的模块。
（5）建一个七段译码的模块
因在系统可编程器件实验箱上的数码管没有经过译码，故要用AHDL语言写一个七段译码的模块，且应考虑数码管为共阳极。数码管上的点(D2、D4、D6)应置Vcc。
四、课程设计所需要仪器
1、计算机一台
2、quartusⅡ软件
3、FPGA开发板
五、设计步骤
1、模块介绍
（1）分频模块：产生1Hz、1KHz、2KHz频率（2）计数器模块：生成60进制、24进制计数器（3）控制模块：按键控制、按键消抖
（4）显示模块：7段数码管显示器，分别显示小时、分钟、秒（5）报时模块：进行整点报时
2、各个模块的设计与仿真
2.1分频模块
CLK晶振频率50MHZ，分成2KHZ,1KHZ,1HZ的信号。基准1HZ信号作为时钟计时的秒计数时钟信号；分频的1KHZ,2KHZ信号用于报时电路的不同声讯。
程序代码：
library ieee;use ieee.std_logic_1164.all;entity fre is port(clk ,sel: in std_logic;clk1hz,clk1khz,clk2khz:out std_logic);end fre;architecture beh of fre is signal data1khz,data2khz,data1hz : std_logic := '0';begin clk1hz <= data1hz;clk1khz <= data1khz;clk2khz <= data2khz;clk1khz_pro : process(clk)--产生1khz信号 variable cnt : integer range 0 to 24999;begin if clk'event and clk='1' then if cnt = 24999 then cnt := 0;data1khz <= not data1khz;else cnt := cnt + 1;end if;end if;end process clk1khz_pro;clk2khz_pro : process(clk)--variable cnt : integer range 0 to 12499;begin if clk'event and clk='1' then if cnt = 12499 then cnt := 0;data2khz <= not data2khz;else cnt := cnt + 1;end if;end if;end process clk2khz_pro;clk1hz_pro : process(data1khz)--variable cnt : integer range 0 to 499;begin if data1khz'event and data1khz='1' then if sel='0' then cnt:=0;else if cnt = 499 then cnt := 0;data1hz <= not data1hz;else cnt := cnt + 1;end if;end if;end if;end process clk1hz_pro;end beh;
输入模块电路图：
产生2khz信号 产生1hz 信号 5 freclkclk1hzclk2khzinst selclk1khz2.2计数器模块
由秒计数器，分计数器，时计数器组成了最基本的数字钟计时电路，两个六十进制计数器与二十四进制计数器组合构成。
程序代码：
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use IEEE.STD_LOGIC_ARITH.ALL;
entity shuzizhong is port(clk_change : in std_logic;s_en,m_en,h_en:in std_logic;sel:in std_logic;secout,minout,hourout :out std_logic;sl,sh,ml,mh,hl,hh:out std_logic_vector(3 downto 0);a:out std_logic_vector(15downto 0));end shuzizhong;architecture behav of shuzizhong is
signal low_rega,high_rega,low_regb,high_regb,low_regc,high_regc :std_logic_vector(3 downto 0):=“0000”;signal sout,mout,hout :std_logic :='0';begin--秒的60进制进制 counter_sec_l : process(clk_change,s_en)begin
sl<=low_rega;sh<=high_rega;ml<=low_regb;mh<=high_regb;hl<=low_regc;hh<=high_regc;6 if clk_change'event and clk_change='1' then if s_en='1' then if low_rega=“1001” then low_rega <= “0000”;else low_rega <= low_rega+'1';end if;end if;end if;end process counter_sec_l;counter_sec_h : process(clk_change,s_en,low_rega)begin if clk_change'event and clk_change='1' then if s_en='1' then if low_rega=“1001” then if high_rega =“0101”then high_rega <= “0000”;else high_rega <= high_rega+'1';end if;end if;end if;end if;end process counter_sec_h;sout <= '1' when low_rega=“1001” and high_rega=“0101” else '0';
----分钟的60进制设置 counter_min_l : process(clk_change,m_en)begin if clk_change'event and clk_change='1' then if m_en='1' then if sout='1'or sel='0' then if low_regb=“1001” then low_regb <= “0000”;else low_regb <= low_regb+'1';end if;end if;end if;end if;end process counter_min_l;counter_min_h : process(clk_change,m_en,low_regb)begin if clk_change'event and clk_change='1' then 7 if sout='1'or sel='0' then if m_en='1' then if low_regb=“1001” then
if high_regb =“0101”then
high_regb <= “0000”;else high_regb <= high_regb+'1';end if;end if;end if;end if;end if;end process counter_min_h;mout <= '1' when low_regb=“1001” and high_regb=“0101”and sout='1' else '0';--小时的24进制设置 counter_hour_l : process(clk_change,h_en)begin if clk_change'event and clk_change='1' then if h_en='1' then if mout='1'or sel='0' then if low_regc=“1001”or hout='1' then low_regc <= “0000”;else low_regc <= low_regc+'1';end if;end if;end if;end if;end process counter_hour_l;counter_hour_h : process(clk_change,h_en,hout)begin if clk_change'event and clk_change='1' then if mout='1'or sel='0' then if h_en='1' then if hout='1' then high_regc<=“0000”;else if low_regc=“1001” then high_regc <= high_regc+'1';end if;end if;end if;8 end if;end if;end process counter_hour_h;hout <= '1' when low_regc=“0011” and high_regc=“0010” else '0';secout<=sout;minout<=mout;hourout<=hout;a<=high_regb&low_regb&high_rega&low_rega;end behav;
输入模块电路图：
shuzizhongclk_changes_enm_enh_enselsecoutminouthouroutsl[3..0]sh[3..0]ml[3..0]mh[3..0]hl[3..0]hh[3..0]a[15..0]inst
2.3控制模块
分五个状态0状态正常计时，按下按键进入下一状态开始调时模式1，按下按键进入调秒模式2，按下按键进入调分模式3，按下按键进入调小时模式4.按下按键恢复正常计时模式。
程序代码：
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity key_press is port(set ,mode: in std_logic;clk1khz,clk1hz: in std_logic;secout,minout: in std_logic;clk_change,clk2hz_en:out std_logic;sel,s_ce,m_ce,h_ce:out std_logic;s_en,m_en,h_en:out std_logic);end key_press;architecture beh of key_press is 9 signal key1,key2:std_logic;signal sce_reg, mce_reg ,hce_reg:std_logic;signal ssl,ssen,mmen,hhen:std_logic;signal con : integer range 0 to 4 :=0;--按键按下（延时）begin
key_press2 : process(set,clk1khz)variable cnt :integer range 0 to 999;begin if set='0' then if clk1khz'event and clk1khz='1'then if cnt=50 and set='0' then cnt :=cnt+1;key2 <= '1';else cnt:=cnt+1;key2 <= '0';end if;end if;else cnt:=0;key2<='0';end if;end process key_press2;key_press1 : process(mode,clk1khz)variable cnt :integer range 0 to 999;begin if mode='0' then if clk1khz'event and clk1khz='1'then if cnt=50 and mode='0' then cnt :=cnt+1;key1 <= '1';else cnt:=cnt+1;key1 <= '0';end if;end if;else cnt:=0;key1<='0';end if;end process key_press1;count : process(key1,key2)begin if key1'event and key1='1' then if con=4 then con<=0;else con<=con+1;end if;end if;10 end process count;con_pro : process(con)begin case con is when 0 => ssl<='1';sce_reg <= '0';ssen <='1';mce_reg <= '0';mmen <='1';hce_reg <= '0';hhen <='1';clk2hz_en <='0';when 1 => ssl<='0';sce_reg <= '0';ssen <='1';mce_reg <= '0';mmen <='1';hce_reg <= '0';hhen <='1';clk2hz_en <='1';when 2 => ssl<='0';sce_reg <= '1';ssen <='1';mce_reg <= '0';mmen <='0';hce_reg <= '0';hhen <='0';clk2hz_en <='1';when 3 => ssl<='0';sce_reg <= '0';ssen <='0';mce_reg <= '1';mmen <='1';hce_reg <= '0';hhen <='0';clk2hz_en <='1';when 4 => ssl<='0';sce_reg <= '0';ssen <='0';mce_reg <= '0';mmen <='0';hce_reg <= '1';hhen <='1';clk2hz_en <='1';when others => ssl<='0';sce_reg <= '0';ssen <='1';mce_reg <= '0';mmen <='1';hce_reg <= '0';hhen <='1';clk2hz_en <='0';end case;end process con_pro;sel_pro : process(ssl)begin case ssl is when '0'=> s_ce<=sce_reg;m_ce<=mce_reg;h_ce<=hce_reg;clk_change<=key2;when '1'=> s_ce<=ssen;11 m_ce<=mmen;h_ce<=hhen;clk_change<=clk1hz;when others=> s_ce<=ssen;m_ce<=secout;h_ce<=minout;clk_change<=clk1hz;end case;end process sel_pro;sel<=ssl;s_en<=ssen;m_en<=mmen;h_en<=hhen;end beh;
输入模块电路图： key_presssetclk_changemodeclk2hz_enclk1khzselclk1hzs_cesecoutm_ceminouth_ces_enm_enh_eninst
2.4数码管分配
程序代码：
library ieee;use ieee.std_logic_1164.all;entity display is port(datain : in std_logic_vector(3 downto 0);dataout : out std_logic_vector(7 downto 0));end display;architecture duan of display is begin process(datain)begin case datain is 12 when “0000” => dataout <=“11000000”;--dp,g,f,e,d,c,b,a when “0001” => dataout <=“11111001”;when “0010” => dataout <=“10100100”;when “0011” => dataout <=“10110000”;when “0100” => dataout <=“10011001”;when “0101” => dataout <=“10010010”;when “0110” => dataout <=“10000010”;when “0111” => dataout <=“11111000”;when “1000” => dataout <=“10000000”;when “1001” => dataout <=“10010000”;when “1010” => dataout <=“10111111”;when “1011” => dataout <=“10000011”;when “1100” => dataout <=“10100111”;when “1101” => dataout <=“10100001”;when “1110” => dataout <=“10000110”;when “1111” => dataout <=“10001110”;when others => null;end case;end process;end;
输入模块电路图：
displaydatain[3..0]dataout[7..0]inst
2.5显示模块
使用七段数码管显示小时、分钟与秒
程序代码：
library ieee;use ieee.std_logic_1164.all;entity scan is port(clk1khz : in std_logic;sl,sh,ml,mh,hl,hh : in std_logic_vector(3 downto 0);clk2hz_en : in std_logic;s_ce,m_ce,h_ce : in std_logic;en_out : out std_logic_vector(7 downto 0);13 dataout : out std_logic_vector(3 downto 0));end scan;architecture beh of scan is signal cnt : integer range 0 to 7;signal en : std_logic_vector(7 downto 0);signal clk2hz : std_logic;signal h_ce_reg,m_ce_reg,s_ce_reg : std_logic;begin h_ce_reg <= not h_ce;m_ce_reg <= not m_ce;s_ce_reg <= not s_ce;cnt_pro : process(clk1khz)begin if clk1khz'event and clk1khz='1' then if cnt = 7 then cnt <= 0;else cnt <= cnt + 1;end if;end if;end process cnt_pro;clk2hz_pro :process(clk1khz)variable c : integer range 0 to 499 := 0;begin if clk1khz'event and clk1khz='1' then if clk2hz_en ='1' then if c =499 then c := 0;clk2hz <= not clk2hz;else c := c + 1;end if;else clk2hz <= '0';end if;end if;end process clk2hz_pro;scan_pro : process(cnt,sl,sh,ml,mh,hl,hh)begin case cnt is when 0 => dataout <= sl;en <= “11111110”;when 1 => dataout <= sh;en <= “11111101”;when 2 => dataout <= ml;en <= “11110111”;when 3 => dataout <= mh;en <= “11101111”;when 4 => dataout <= hl;en <= “10111111”;14 when 5 => dataout <= hh;en <= “01111111”;when 6 => dataout <= “1010”;en <= “11111011”;when 7 => dataout <= “1010”;en <= “11011111”;when others => null;end case;end process scan_pro;
en_out <= en or((clk2hz & clk2hz)or(h_ce_reg & h_ce_reg))& clk2hz &((clk2hz & clk2hz)or(m_ce_reg & m_ce_reg))& clk2hz &((clk2hz & clk2hz)or(s_ce_reg & s_ce_reg));end beh;
输入模块电路图：
scanclk1khzen_out[7..0]sl[3..0]dataout[3..0]sh[3..0]ml[3..0]mh[3..0]hl[3..0]hh[3..0]clk2hz_ens_cem_ceh_ceinst
2.6报时模块
利用蜂鸣器进行整点报时
程序代码：
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use IEEE.STD_LOGIC_ARITH.ALL;--整点报时 entity baoshi is port(clk1khz,clk2khz : in std_logic;a:in std_logic_vector(15 downto 0);sel:in std_logic;bell:out std_logic);end baoshi;architecture zhong of baoshi is signal c1,ring:std_logic;begin ring_bell :process(clk1khz,clk2khz)15 begin case a is when “***0” => c1<=clk1khz;when “***0” => c1<=clk1khz;when “***0” => c1<=clk1khz;when “***0” => c1<=clk1khz;when “***0” => c1<=clk1khz;when “***0” => c1<=clk2khz;when “***0” => c1<=clk2khz;when others => c1<='0';end case;end process ring_bell;
bs: process(c1)begin if sel='1' then if c1='1' then ring<='0';else ring<='1';end if;end if;end process bs;bell<=ring;
end zhong;
输入模块电路图：
baoshiclk1khzbellclk2khza[15..0]selinst
整体模块电路图
displayshuzizhongs_enm_enh_enselclk_changes_enm_enh_enselsecoutminouthouroutsl[3..0]sh[3..0]ml[3..0]mh[3..0]hl[3..0]hh[3..0]setmodefreclkINPUTVCCINPUTVCCdata[3..0]datain[3..0]secoutminoutinst1scanclk1khzclk1khzsl[3..0]sh[3..0]ml[3..0]mh[3..0]hl[3..0]a[15..0]dataout[7..0]OUTPUTdataout[7..0]en_out[7..0]dataout[3..0]OUTPUTen_out[7..0]data[3..0]key_presssetclk1khzmodeclk1khzclk1hzsecoutminoutclk_changeclk2hz_ensels_cem_ceh_ces_enm_enh_eninst6s_enm_enh_enselinst7a[15..0]INPUTVCChh[3..0]clk2hz_ens_cem_ceh_ceinst4baoshiclk1khzclk2khza[15..0]selclk1khzbellclk2khza[15..0]sel++selclkclk1hzselclk1khzclk2khzinst2clk1khzclk2khzsecoutminoutOUTPUTbellinst
六、调试中遇到的问题及解决的方法：
1、编程时，经常导致语法错误，如：“；”没有写上，变量类型没有预先标明，前后变量名字由于缺少一个或多一个字母而导致出错。解决办法：对照错误，认真检查程序，看哪个地方的标点，变量没有写上或标明。
2、进行编译或波形仿真时，经常得到的不是预想中的结果。
解决办法：将需要编译或进行仿真的实体文件置顶，经检错无误后，进行波形仿真，在仿真之前需要合理设置仿真结束时间和信号周期。
3、在控制时间的显示的时候，由于变量太多多发现不能完全的控制住变量，导致显示的时候出现了乱码，数码管显示不正常 解决办法：减少变量，仔细推敲，合理命名。
七、心得体会
一个多星期的课程设计让我受益匪浅，也让我真正明白理论与实践相结合的重要性。通过具体实践才能让自己清楚哪些知识已经掌握，哪些知识仍需巩固加强。与此同时，我也对EDA以及VHDL语言有了进一步了解，对于其结构、语法、功能等认识不少。当然，我目前所做的还仅仅只是一些基本操作，要想真正将其融会贯通还需要今后更多的学习与实践。虽然只是一个小设计，我却也从中学到了不少设计流程和一些相关问题。设计是一个十分严谨的过程，容不得随意和马虎。要想快速而高效地完成一项设计，必须先有一个清晰明了的设计思路，设想好一个整体框架，然后在此基础上，逐渐将各个部分功能进行完善。在设计的过程中，也曾遇到不少困难，但正所谓坚持就是胜利，要想取得成功，必须要有努力付出，这样所取得的结果才更有意义。
第三篇：EDA实现多功能数字钟
EDA实现多功能数字钟
实
验 报 告
专业班级：
学生姓名：
学生学号：
目录
一、内容摘要
二、实验要求
三、各底层模块设计
四、总体方案
五、心得体会
一、实验内容
利用 QuartusII 软件，结合所学的数字电路的知识设计一个 24 时多功能数 字钟，具有正常分、秒计时，动态显示的功能。分析整个电路的工作原理，分别说明各子模块的设计原理和调试、仿真、编 程的过程。
二、实验任务：
用 FPGA 器件和 EDA 技术实现多功能数字钟的设计
已知条件：
1、MAX+Plus 软件
2、FPGA 实验开发装置
基本功能：
1、以数字形式显示时、分、秒的时间；
2、小时计数器为 24 进制；
3、分、秒计数器为 60 进制。
三、底层模块设计（电路原理图及仿真）
1、小时计数器为24进制 电路原理图
仿真图
封装图
2、分、秒计时器都为60进制 电路原理图
仿真图
封装图
四、总体方案
按照上述实验要求，本次电子数字时钟实验，通过两个模 60 计数器及一个模 24 计数器级联既可以实现计时模块。多功能数字钟的主体部分 电路原理图
仿真图
封装图
五、心得体会
刚刚开始觉得做这个电子实验报告挺难的，因为对软件的不熟悉和对这个实验操作的也不熟悉，对着老师给的资料也做了很长时间，就是仿真的时候有些该注意的没有注意，导致仿真失败，但是后来还是自己慢慢拿的请教同学、老师哪里出了问题，后来才做出来了，把60进制的做出来了，后来的24进制按照老师给的电路原理图也成功了仿真出来，我用了很长时间才编写出来，现在看看，也没有那么难了。同时请教老师，和同学、通过实验掌握一些逻辑组合器件的基本功能和用法。总之，我很感谢这次实验可以给我这样的机会，这个实验给了我很对的收获，我相信这会对我以后的学习很有帮助。
第四篇：eda 实现多功能数字钟
一、标题：EDA实现多功能数字钟
二、任务书：设计要求是用FPGA器件和EDA技术实现多功能数字钟的设计，⑴ 控制功能包括①以数字形式显示时、分、秒的时间；②小时计数器为24进制；③分、秒计数器为60进制；④有两个使能端起到校时、校分的作用，同时按无效；⑤每小时的59分51、53、55、57、59分别以四长声一短声进行模拟电台仿真；⑥让信号灯在晚上19点至早上5点亮；⑵ 在Max＋plusⅡ软件系统平台上建立多功能数字钟电路的顶层电路文件并完成编译和仿真，并对器件进行下载检查。
三、关键词：数字钟 原理电路 编译 仿真 下载
四、数字钟电路系统的组成框图：
五、各功能模块设计、仿真波形及其分析说明：
1、小时计时模块：
仿真波形：
分析说明：
当小时的高四位为0、1时，小时的低四位为九时，在下一个时钟的上跳延来了之后，高四位加一；当小时的高四位为2，同时低四位为3时，小时的高低四位都清零。实现从00到23的循环计数。
2、分钟计时模块：
仿真波形：
分析说明：
当分钟的高四位为0、1、2、3、4时，小时的低四位为九时，在下一个时钟的上跳延来了之后，高四位加一；当分钟的高四位为5时，同时低四位为9时，分钟的高低四位都清零，实现从00到59的循环计数。
3、秒计时模块（与分计时模块相同）；
4、校时、校分模块：
仿真波形：
分析说明：
SWM、SWH两开关先设置1，秒时钟，分时钟，小时时钟分别设置为不同频率的时钟，当开关SWM置0即按下时，秒时钟CPS对分钟进行校对，即如图所示CPM在SWM为0时频率与CPS相同；同理，当SWH为0时用秒时钟对小时进行校对，即CPH在SWH为0时频率与CPS相同。当SWM、SWH都不为0时，分钟、小时正常计时。
5、整点报时模块：
仿真波形：
分析说明：
为实现时钟在59分51秒53秒55秒57秒时，以低音报时，当为59分59秒时以高音报时；所以将M[7..0]从高位到低位设置为0101 1001转换成十进制即为59分，秒的十位都为5所以S7到S4设置为0101，秒的个位1、3、5、7、9，即0001、0011、0101、0111、1001，从S3到S0只有当S3设置为1的时候秒个位为9，通过分频以1000HZ输出以实现高音报时；1、3、5、7时S0都为0，为能同时确定1、3、5、7则将S0设置为0，S1、S2则为任意。如波形所示，S3取一段设置为1时，输出FU变为1000HZ的高频报时，其余状态一致为500HZ低频报时，从而实现预期情况。
6、时段控制模块：
仿真波形：
分析说明：
从19点到凌晨5点（含5点），灯亮，即完成时段控制。
六、顶层逻辑电路图、仿真波形及分析结论：
建立一个顶层文件如图：
仿真波形如下：
分析结论：
经仿真波形分析①走时正常；②能〝校时〞〝校分〞；③整点报时；④时段控制到位。功能完全符合设计要求，可以下载。
七、定义芯片管脚号（列表示意）及下载过程：
1、由于提供的实验箱的七段显示器是扫描形式工作，需要进行译码以及选择扫描，需添加模块：
该模块有三部分组成，包括一个8进制计数器，一个3-8数据选择器及七段显示译码器：
将该模块连入最后的顶层文件中，即可进行下载工作。
2、按键扫描模块：由于试验箱提供的按键系统为4*4扫描矩阵，需将横向或纵向按键设置0或1，该模块只需要在顶层文件中接4个output出来接地，如图：
3、分配输入、输出信号在器件上的引脚号：
4、引脚分配表：
5、对器件进行下载：
选MAX+plus II/Programmer，弹出编程对话框，如图：
检查编程文件名和器件，正确，接上硬件后，点击器件编程。即完成下载。
八、课程设计中遇到问题及解决方法
Q1：下载后，秒钟不进位
A：检查原理电路发现输入输出接错位，经更正正常； Q2：到59分51秒等不闹钟
A：检查蜂鸣器是否接错管脚，下载器上套线是否接好，最后发现是套线的问题，解决后，正常鸣叫。
九、课程设计项目最终结论
通过各模块级联最后成功下载，实现了两个使能对分秒校时，整点仿电台报时以及时段控制的多功能数字钟。
十、心得体会：
实验过程中最然遇到了很多困难，从画图到理解电路图，还有接触没有接触过的下载，把纸上的东西用到了硬件中，质的改变。看到成功的数字钟，很有成就感。好像听到的蜂鸣声是从未听到过的美妙乐曲。课设给我们指引了又一工作方向，培养对这些的兴趣，对以后工作应该很有帮助，所以坚定了我课后还要多看书多学习这方面知识的信念。
十一、参阅教材及文献：
《电子线路实验设计仿真讲义》
按钮，直接对
第五篇：多功能数字钟课程设计VHDL代码书上程序改
library ieee;use ieee.std_logic_1164.all;entity clock is port(clk1hz:in std_logic;--1hz脉冲--clk100:in std_logic;--100hz脉冲--weekclk:in std_logic;--星期调整脉冲--start_stop:in std_logic;--秒表启动/停止控制--reset:in std_logic;--秒表复位--adclk:in std_logic;--校时脉冲--setselect:in std_logic;--调整位选择脉冲--mode:in std_logic;--功能选择脉冲--showdate:in std_logic;--日期显示--dis:out std_logic_vector(23 downto 0);--显示输出--glisten:out std_logic_vector(5 downto 0);--闪烁指示--weekout:out std_logic_vector(3 downto 0);--星期输出--qh:out std_logic--整点报时--);end clock;architecture arch of clock is component adjust
port（adclk: in std_logic;
data_in: out std_logic_vector(7 downto 0));end component;component control
port（setclk: in std_logic;
setlap: out std_logic_vector(1 downto 0);
mode: in std_logic;
module: out std_logic_vector(2 downto 0));end component;component weekcounter
port（clk: in std_logic;
clk2: in std_logic;
q: out std_logic_vector(3 downto 0));end component;component stopwatch
port（clk: in std_logic;
reset: in std_logic;
start_stop: in std_logic;
centsec: out std_logic_vector(7 downto 0);
sec: out std_logic_vector(7 downto 0);
min: out std_logic_vector(7 downto 0));end component;component h_m_s_count
port（clk: in std_logic;
set: in std_logic;
setlap: in std_logic_vector(1 downto 0);
d:in std_logic_vector(7 downto 0);
sec:out std_logic_vector(7 downto 0);
min:out std_logic_vector(7 downto 0);
hour:out std_logic_vector(7 downto 0);
qh:out std_logic;
qc: out std_logic);end component;component y_m_d_count
port（clk: in std_logic;
set: in std_logic;
setlap: in std_logic_vector(1 downto 0);
data_in: in std_logic_vector(7 downto 0);
day: out std_logic_vector(7 downto 0);
month: out std_logic_vector(7 downto 0);
year: out std_logic_vector(7 downto 0));end component;component display
port（module: in std_logic_vector(2 downto 0);
showdate:in std_logic;
clk:in std_logic;
setlap:in std_logic_vector(1 downto 0);
watch: in std_logic_vector(23 downto 0);
time:in std_logic_vector(23 downto 0);
date:in std_logic_vector(23 downto 0);
dis: out std_logic_vector(23 downto 0);
glisten:out std_logic_vector(5 downto 0));end component;signal data_in,mcentsec,msec,mmin,ssec,smin,shour,sdate,smonth,syear:std_logic_vector(7 downto 0);signal setlap:std_logic_vector(1 downto 0);signal module:std_logic_vector(2 downto 0);signal qc:std_logic;signal watch,time,date:std_logic_vector(23 downto 0);begin u1:adjust port map(adclk,data_in);u2:control port map(setselect,setlap,mode,module);u3:stopwatch port map(clk100,reset,start_stop,mcentsec,msec,mmin);u4:h_m_s_count port map(clk1hz,module(1),setlap,data_in,ssec,smin,shour,qh,qc);u5:y_m_d_count port map(qc,module(2),setlap,data_in,sdate,smonth,syear);u6:display port map(module,showdate,clk1hz,setlap,watch,time,date,dis,glisten);u7:weekcounter port map(qc,weekclk,weekout);watch<=mmin&msec&mcentsec;time<=shour&smin&ssec;date<=syear&smonth&sdate;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity adjust is
port（adclk: in std_logic;
data_in: out std_logic_vector(7 downto 0));end adjust;architecture arch of adjust is signal temp2,temp1:std_logic_vector(3 downto 0);begin process(adclk)begin if rising_edge(adclk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“1001” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;end if;end if;data_in<=temp2&temp1;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity control is
port（setclk: in std_logic;--调整脉冲--
setlap: out std_logic_vector(1 downto 0);--调整位选择脉冲--
mode: in std_logic;--功能选择脉冲--
module: out std_logic_vector(2 downto 0)--功能输出--);end control;architecture arch of control is signal ssetlap:std_logic_vector(1 downto 0);signal s:std_logic_vector(3 downto 0);begin process(mode,setclk)begin if mode='1'then ssetlap<=“00”;elsif rising_edge(setclk)then if ssetlap=“10”then ssetlap<=“00”;else ssetlap<=ssetlap+'1';end if;end if;end process;setlap<=ssetlap;process(mode)begin if rising_edge(mode)then case s is when“0001”=>s<=“0010”;when“0010”=>s<=“0100”;when“0100”=>s<=“1000”;when“1000”=>s<=“0001”;when others=>s<=“0010”;end case;end if;end process;module<=s(3 downto 1);end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity counter60 is
port（clk: in std_logic;--计数脉冲--
clr: in std_logic;--复位--
q: out std_logic_vector(7 downto 0);--计数值--
qc:out std_logic--进位输出--);end counter60;architecture arch of counter60 is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clr,clk)begin if clr='1'then temp1<=“0000”;temp2<=“0000”;elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else temp1<=temp1+'1';end if;if temp2=“0101” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;qc<='1';else qc<='0';end if;end if;q<=temp2&temp1;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity counter99 is
port（clk: in std_logic;--100vhz计数脉冲--
en: in std_logic;--计数使能--
clr: in std_logic;--复位--
q: out std_logic_vector(7 downto 0);--计数值--
qc: out std_logic--进位--);end counter99;
architecture arch of counter99 is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clr,clk)begin if clr='1'then temp1<=“0000”;temp2<=“0000”;elsif rising_edge(clk)then if en='1' then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“1001” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;qc<='1';else qc<='0';end if;end if;end if;q<=temp2&temp1;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity daycounter is
port（clk: in std_logic;--计数脉冲--
set: in std_logic;--调整信号--
day_in: in std_logic_vector(7 downto 0);--调整输入--
day_out: out std_logic_vector(7 downto 0);--天输出--
qc: out std_logic;--进位--
day28: in std_logic;--该位为1表示该月为28天--
day29: in std_logic;--该位为1表示该月为29天--
day30: in std_logic;--该位为1表示该月为30天--
day31: in std_logic--该位为1表示该月为31天--);end daycounter;architecture arch of daycounter is signal temp1,temp2:std_logic_vector(3 downto 0);signal days:std_logic_vector(7 downto 0);begin days<=“00101000” when day28='1'else
“00101001”when day29='1'else
“00110000”when day30='1'else
“00110001”when day31='1'else
“00000000”;process(clk,set,day_in,days)begin if set='1' then temp2<=day_in(7 downto 4);temp1<=day_in(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else temp1<=temp1+'1';end if;if temp2&temp1=days then temp2<=“0000”;temp1<=“0001”;qc<='1';else qc<='0';end if;end if;end process;day_out<=temp2&temp1;end arch;library ieee;use ieee.std_logic_1164.all;entity days_control is port（month: in std_logic_vector(7 downto 0);--月份--
year2: in std_logic;--年份高位数字bcd码最低位--
year1: in std_logic_vector(1 downto 0);--年份低位数字bcd码末两位--
day28: out std_logic;--该位为1表示该月为28天--day29: out std_logic;--该位为1表示该月为29天--
day30: out std_logic;--该位为1表示该月为30天--
day31: out std_logic--该位为1表示该月为31天--);end days_control;architecture arch of days_control is begin process(month,year2,year1)begin case month is when “00000001”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00000010”=>if(year2='0'and year1=“00”)or(year2='1'and year1=“10”)then
day28<='0';day29<='1';day30<='0';day31<='0';
else
day28<='1';day29<='0';day30<='0';day31<='0';
end if;when “00000011”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00000100”=>day28<='0';day29<='0';day30<='1';day31<='0';when “00000101”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00000110”=>day28<='0';day29<='0';day30<='1';day31<='0';when “00000111”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00001000”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00001001”=>day28<='0';day29<='0';day30<='1';day31<='0';when “00010000”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00010001”=>day28<='0';day29<='0';day30<='1';day31<='0';when “00010010”=>day28<='0';day29<='0';day30<='0';day31<='1';when others=>day28<='0';day29<='0';day30<='0';day31<='1';end case;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity display is
port（module: in std_logic_vector(2 downto 0);--功能选择--
showdate:in std_logic;--显示日期--
clk:in std_logic;--闪烁脉冲--
setlap:in std_logic_vector(1 downto 0);--闪烁位选择--
watch: in std_logic_vector(23 downto 0);--秒表计数值输入--
time:in std_logic_vector(23 downto 0);--时分秒计数值输入--date:in std_logic_vector(23 downto 0);--年月日计数值输入--
dis: out std_logic_vector(23 downto 0);--显示输出--
glisten:out std_logic_vector(5 downto 0)--闪烁输出--);end display;architecture arch of display is begin process(module,showdate,watch,time,date)begin if showdate='1'then dis<=date;else case module is when“001”=>dis<=watch;when“010”=>dis<=time;when“100”=>dis<=date;when others=>dis<=time;end case;end if;end process;process(clk,module,setlap)begin if module=“010”or module=“100”then case setlap is when“00”=>glisten(1 downto 0)<=clk&clk;
glisten(5 downto 2)<=“0000”;when“01”=>glisten(3 downto 2)<=clk&clk;
glisten(5 downto 4)<=“00”;
glisten(1 downto 0)<=“00”;when“10”=>glisten(5 downto 4)<=clk&clk;
glisten(3 downto 0)<=“0000”;when others=>glisten<=“000000”;end case;else glisten<=“000000”;end if;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity dmux is
port（set:in std_logic;--调整信号--
setlap: in std_logic_vector(1 downto 0);--调整位选择--
d: in std_logic_vector(7 downto 0);--调整输入--
set1:out std_logic;
set2:out std_logic;
set3:out std_logic;
q1: out std_logic_vector(7 downto 0);
q2: out std_logic_vector(7 downto 0);
q3: out std_logic_vector(7 downto 0));end dmux;architecture arch of dmux is begin process(set,setlap,d)begin if set='1' then case setlap is when“00”=>set1<='1';set2<='0';set3<='0';
q1<=d;when“01”=>set1<='0';set2<='1';set3<='0';
q2<=d;when“10”=>set1<='0';set2<='0';set3<='1';
q3<=d;when others=>set1<='0';set2<='0';set3<='0';end case;else set1<='0';set2<='0';set3<='0';end if;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity h_m_s_count is
port（clk: in std_logic;--1hz脉冲--
set: in std_logic;--调整信号--
setlap: in std_logic_vector(1 downto 0);--调整位选择--
d:in std_logic_vector(7 downto 0);--调整输入--
sec:out std_logic_vector(7 downto 0);--秒输出--
min:out std_logic_vector(7 downto 0);--分输出--
hour:out std_logic_vector(7 downto 0);--小时输出--
qh:out std_logic;--整点报时--
qc: out std_logic--进位--);end h_m_s_count;architecture arch of h_m_s_count is component sec_mincounter
port（clk: in std_logic;
set:in std_logic;
d:in std_logic_vector(7 downto 0);
q:out std_logic_vector(7 downto 0);
qc:out std_logic);end component;component hourcounter port（clk: in std_logic;
set:in std_logic;
d:in std_logic_vector(7 downto 0);
q: out std_logic_vector(7 downto 0);
qc:out std_logic);end component;component dmux
port（set:in std_logic;
setlap: in std_logic_vector(1 downto 0);
d: in std_logic_vector(7 downto 0);
set1:out std_logic;
set2:out std_logic;
set3:out std_logic;
q1: out std_logic_vector(7 downto 0);
q2: out std_logic_vector(7 downto 0);
q3: out std_logic_vector(7 downto 0));end component;signal secset,minset,hourset: std_logic;signal secin,minin,hourin:std_logic_vector(7 downto 0);signal qcsec,qcmin,qchour: std_logic;begin u1:dmux port map(set,setlap,d,secset,minset,hourset,secin,minin,hourin);u2:sec_mincounter port map(clk,secset,secin,sec,qcsec);u3:sec_mincounter port map(qcsec,minset,minin,min,qcmin);u4:hourcounter port map(qcmin,hourset,hourin,hour,qchour);qh<=qcmin;qc<=qchour;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity hourcounter is
port（clk: in std_logic;--计数脉冲--
set:in std_logic;--调整信号--
d:in std_logic_vector(7 downto 0);--调整时间--
q: out std_logic_vector(7 downto 0);--小时输出--
qc:out std_logic--进位--);end hourcounter;architecture arch of hourcounter is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clk,set)begin if set='1'then temp2<=d(7 downto 4);temp1<=d(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“0010” and temp1=“0100” then temp1<=“0000”;temp2<=“0000”;qc<='1';else qc<='0';end if;end if;end process;q<=temp2&temp1;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity monthcounter is
port（clk: in std_logic;--计数脉冲--
set: in std_logic;--调整信号--
month_in: in std_logic_vector(7 downto 0);--调整输入--
month_out: out std_logic_vector(7 downto 0);--月输出--
qc: out std_logic--进位--);end monthcounter;architecture arch of monthcounter is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clk,set,month_in)begin if set='1' then temp2<=month_in(7 downto 4);temp1<=month_in(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“0001”and temp1=“0010” then temp2<=“0000”;temp1<=“0001”;qc<='1';else qc<='0';end if;end if;end process;month_out<=temp2&temp1;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity sec_mincounter is port（clk: in std_logic;--计数脉冲--
set:in std_logic;--调整信号--
d:in std_logic_vector(7 downto 0);--调整时间输入--
q:out std_logic_vector(7 downto 0);--分和秒输出--
qc:out std_logic--进位--);end sec_mincounter;architecture arch of sec_mincounter is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clk,set)begin if set='1'then temp2<=d(7 downto 4);temp1<=d(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“0101” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;qc<='1';else qc<='0';end if;end if;end process;q<=temp2&temp1;end arch;library ieee;use ieee.std_logic_1164.all;entity stopwatch is port（clk: in std_logic;--100hz脉冲--
reset: in std_logic;--复位--
start_stop: in std_logic;--启动/停止--
centsec: out std_logic_vector(7 downto 0);--百分秒输出，当超过60分转为秒--
sec: out std_logic_vector(7 downto 0);--秒输出，当超过60分转为分--
min: out std_logic_vector(7 downto 0)--分输出，当超过60分转为小时--);end stopwatch;architecture arch of stopwatch is component counter99 port（clk: in std_logic;
en: in std_logic;
clr: in std_logic;
q: out std_logic_vector(7 downto 0);
qc: out std_logic);end component;component counter60 port（clk: in std_logic;
clr: in std_logic;
q: out std_logic_vector(7 downto 0);
qc: out std_logic);end component;signal qc1,qc2,qc3,qc4,flag:std_logic;signal tcentsec,tsec,tmin,thour:std_logic_vector(7 downto 0);begin u1:counter99 port map(clk,start_stop,reset,tcentsec,qc1);u2:counter60 port map(qc1,reset,tsec,qc2);u3:counter60 port map(qc2,reset,tmin,qc3);u4:counter60 port map(qc3,reset,thour,qc4);process(qc3)begin if rising_edge(qc3)then flag<='1';end if;if flag='1' then centsec<=tsec;sec<=tmin;min<=thour;else centsec<=tcentsec;sec<=tsec;min<=tmin;end if;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity weekcounter is
port（clk: in std_logic;--天脉冲--
clk2: in std_logic;--外部星期调整脉冲--
q: out std_logic_vector(3 downto 0)--星期输出--);end weekcounter;architecture arch of weekcounter is signal temp:std_logic_vector(3 downto 0);signal cp:std_logic;begin cp<=clk or clk2;process begin wait until rising_edge(cp);if temp=“0111” then temp<=“0001”;else
temp<=temp+'1';end if;q<=temp;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity y_m_d_count is
port（clk: in std_logic;--计数脉冲--
set: in std_logic;--调整信号--
setlap: in std_logic_vector(1 downto 0);--调整位选择--
data_in: in std_logic_vector(7 downto 0);--调整输入--
day: out std_logic_vector(7 downto 0);--日输出--
month: out std_logic_vector(7 downto 0);--月输出--
year: out std_logic_vector(7 downto 0)--年输出--);end y_m_d_count;architecture arch of y_m_d_count is component daycounter
port（clk: in std_logic;
set: in std_logic;
day_in: in std_logic_vector(7 downto 0);
day_out: out std_logic_vector(7 downto 0);
qc: out std_logic;
day28: in std_logic;
day29: in std_logic;
day30: in std_logic;
day31: in std_logic);end component;component monthcounter
port（clk: in std_logic;
set: in std_logic;
month_in: in std_logic_vector(7 downto 0);
month_out: out std_logic_vector(7 downto 0);
qc: out std_logic);end component;component yearcounter
port（clk: in std_logic;
set: in std_logic;
year_in: in std_logic_vector(7 downto 0);
year_out: out std_logic_vector(7 downto 0));end component;component dmux
port（set:in std_logic;
setlap: in std_logic_vector(1 downto 0);
d: in std_logic_vector(7 downto 0);
set1:out std_logic;
set2:out std_logic;
set3:out std_logic;
q1: out std_logic_vector(7 downto 0);
q2: out std_logic_vector(7 downto 0);
q3: out std_logic_vector(7 downto 0));end component;component days_control
port（month: in std_logic_vector(7 downto 0);
year2: in std_logic;
year1: in std_logic_vector(1 downto 0);
day28: out std_logic;
day29: out std_logic;
day30: out std_logic;
day31: out std_logic);end component;signal dayset,monthset,yearset: std_logic;signal qcday,qcmonth: std_logic;signal dayin,monthin,yearin: std_logic_vector(7 downto 0);signal smonth,syear:std_logic_vector(7 downto 0);signal day28,day29,day30,day31:std_logic;begin u1:dmux port map(set,setlap,data_in,dayset,monthset,yearset,dayin,monthin,yearin);u2:daycounter port map(clk,dayset,dayin,day,qcday,day28,day29,day30,day31);u3:monthcounter port map(qcday,monthset,monthin,smonth,qcmonth);u4:yearcounter port map(qcmonth,yearset,yearin,syear);u8:days_control port map(smonth,syear(4),syear(1 downto 0),day28,day29,day30,day31);month<=smonth;year<=syear;
end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity yearcounter is
port（clk: in std_logic;--计数脉冲--
set: in std_logic;--调整信号--
year_in: in std_logic_vector(7 downto 0);--调整输入--
year_out: out std_logic_vector(7 downto 0)--年输出--);end yearcounter;architecture arch of yearcounter is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clk,set,year_in)begin if set='1' then temp2<=year_in(7 downto 4);temp1<=year_in(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“1001” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;end if;end if;end process;year_out<=temp2&temp1;end arch;
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