第一篇：广播电台整点报时
周一至周五整点报时
06：00一日之计在于晨，一天中的美好时光从早上开始。
07：00早上七点，新的一天找到新的动力。
07：00匆忙的早晨一袋牛奶、一只鸡蛋加上几片面包它就能为您提供一上午的能量。现在是早上7点。08：00在工作和学习开始之前，喝杯水，它能促进代谢，帮助醒脑。现在是早上8点。
09：00繁忙而紧张的工作需要理清头绪，今天你做到了吗？现在是北京时间9点整
10：00工作中带着微笑，让微笑感染周围的人。现在是北京时间上午10点整。
11：00忙了一上午，抽个空，远眺下远方的绿色让眼睛得到适当的休息，现在是上午十一点。12：00又是一个交通小高峰，回家路上注意安全！现在是北京时间中午12点整。
13：00午休小憩一会儿，下午的工作将事半功倍。现在是北京时间下午1点整。
14：00喝杯浓茶，振作精神，下午两点，有音乐的陪伴让工作更顺畅。
15：00事都有着多面性，换个方向，或许你能发现更多答案。现在是下午三点。
16：00在忙碌中找寻休憩，在平淡中找寻快乐。多一些快乐，少一丝束缚。现在是下午四点 17：00关爱他人，从小事开始。现在是北京时间下午5点整。
18：00下班高峰期，注意行车安全。现在是北京时间旁晚6点。
19：00关注时事动态，了解新闻大事，新闻联播更精彩。
20：00在城市的夜空下，欣赏喧嚣的夜晚，现在是晚上八点。
21：00让时间承载记忆，让岁月留下印记。现在是北京时间晚上9点整。
22：00喝一杯牛奶，融化一天的疲倦。现在是北京时间晚上10点整。
23：00寂静的深夜，依旧有好声音陪伴。现在是北京时间晚上11点整。
24：00静谧的午夜，道一声：“晚安"。现在是晚上12点。
工作张弛有度，生活追求品质，
第二篇：多功能数字钟课程设计整点报时与闹钟功能VHDL代码
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity timkeeper is
Port(up,setpin,upclk,settime,run : in std_logic;
a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0);
result: out std_logic);end timkeeper;
architecture Behavioral of timkeeper is
component h_m_s_time port（clk0,clk1,ce : in std_logic;
sec0,sec1 : buffer std_logic_vector(3 downto 0);
lock : in std_logic_vector(2 downto 0);
up : in std_logic;min0,min1 : buffer std_logic_vector(3 downto 0);hour0,hour1 : buffer std_logic_vector(3 downto 0);ov : out std_logic);end component;component date port（clk0,clk1,ce : in std_logic;
lock : in std_logic_vector(2 downto 0);
up : in std_logic;
mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);
date0,date1 : buffer std_logic_vector(3 downto 0);
ov : out std_logic);
end component;component month_year port（clk0,clk1,ce : in std_logic;
lock : in std_logic_vector(2 downto 0);
up : in std_logic;
mon0,mon1 : buffer std_logic_vector(3 downto 0);
year0,year1 : buffer std_logic_vector(3 downto 0));end component;component LED_disp port（lock : in std_logic_vector(2 downto 0);
sec0,sec1,min0,min1,hour0,hour1 : in std_logic_vector(3 downto 0);
date0,date1,mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);
a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0));end component;component alarm Port（hour1,hour0,min1,min0,sec1,sec0 : in std_logic_vector(3 downto 0);
settime,run : in std_logic;
result : out std_logic);end component;
signal Tlock:std_logic_vector(2 downto 0);signal Tsecond_wave:std_logic;signal Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1:std_logic_vector(3 downto 0);signal Tdate0,Tdate1,Tmon0,Tmon1,Tyear0,Tyear1:std_logic_vector(3 downto 0);signal Tovday,Tovmonth:std_logic;signal vcc:std_logic;begin vcc<='1';process(setpin)begin
if rising_edge(setpin)then
Tlock<=Tlock+'1';
end if;
end process;
u2:h_m_s_time port map(Tsecond_wave,upclk,vcc,Tsec0,Tsec1,Tlock,up，Tmin0,Tmin1,Thour0,Thour1,Tovday);u3:date port map(Tovday,upclk,vcc,Tlock,up,Tmon0,Tmon1,Tyear0,Tyear1，Tdate0,Tdate1,Tovmonth);u4:month_year port map(Tovmonth,upclk,vcc,Tlock,up,Tmon0,Tmon1,Tyear0,Tyear1);u5:LED_disp port map(Tlock,Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1,Tdate0，Tdate1,Tmon0,Tmon1,Tyear0,Tyear1,a0,a1,b0,b1,c0,c1);u6:alarm port map(Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1,settime,run ,result);end Behavioral;
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;use work.pac.all;entity alarm is
Port(hour1,hour0,min1,min0,sec1,sec0 : in std_logic_vector(3 downto 0);
settime,run : in std_logic;
result : out std_logic);end alarm;
architecture Behavioral of alarm is signal dhour1,dhour0,dmin1,dmin0,dsec1,dsec0:std_logic_vector(3 downto 0);begin p0:process(settime)
begin
if settime='1'then
dhour1<=hour1;
dhour0<=hour0;
dmin1<=min1;
dmin0<=min0;
dsec1<=sec1;
dsec0<=sec0;
end if;
end process p0;p1:process(run)
begin if run='1'then
if hour1=dhour1 and hour0=dhour0 and min1=dmin1 and min0=dmin0 and sec1=dsec1 and sec0 =dsec0 then
result<='1';
else result<='0';
end if;else result<='0';end if;
end process p1;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;use work.pac.all;entity date is
Port(clk0,clk1,ce : in std_logic;
lock : in std_logic_vector(2 downto 0);
up : in std_logic;
mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);
date0,date1 : buffer std_logic_vector(3 downto 0);
ov : out std_logic);end date;
architecture Behavioral of date is signal tempy0:std_logic_vector(1 downto 0);signal tempy1,clk:std_logic;signal Td0,Td1:std_logic_vector(3 downto 0);begin tempy0<=year0(1 downto 0);tempy1<=year1(0);Td0<=date0;Td1<=date1;u1:process(lock,clk0,clk1)
begin
if(lock=“000” or lock=“001”)then clk<=clk0;
else clk<=clk1;
end if;
end process u1;
u2:process(clk,ce)
begin
if rising_edge(clk)then
if(ce='1')then
if(lock=“000”)or(lock=“001”)or(lock=“100” and up='1')then
if(mon0=“0010” and mon1=“0000”)then
Feb_add_day(Td0,Td1,tempy0,tempy1,date0,date1);
elsif((mon0=“0001” and mon1=“0000”)or(mon0=“0011” and or(mon0=“0101” and mon1=“0000”)or(mon0=“0111” and mon1=“0000”)
mon1=“0000”)
or(mon0=“1000” and mon1=“0000”)or(mon0=“0000”and mon1=“0001”)or(mon0=“0010” and mon1=“0001”))then
oddmonth_add_day(Td0,Td1,date0,date1);
else evenmonth_add_day(Td0,Td1,date0,date1);
end if;
end if;
if(lock=“100” and up='0')then
if(mon0=“0010” and mon1=“0000”)then
Feb_sub_day(Td0,Td1,tempy0,tempy1,date0,date1);
elsif((mon0=“0001” and mon1=“0000”)or(mon0=“0011” and mon1=“0000”)or(mon0=“0101” and mon1=“0000”)or
(mon0=“0111” and mon1=“0000”)or(mon0=“1000” and mon1=“0000”)or(mon0=“0000” and mon1=“0001”)or(mon0=“0010”
and mon1=“0001”))then
oddmonth_sub_day(Td0,Td1,date0,date1);
else evenmonth_sub_day(Td0,Td1,date0,date1);
end if;
end if;
end if;
end if;
end process u2;
u3:process(ce)
begin
if rising_edge(clk)then
if(lock/=“000” and lock/=“001”)then
ov<='0';
elsif(ce='1')then
if(mon0=“0010” and mon1=“0000”)then
if((tempy1='0' and tempy0=“00”)or(tempy1='1' and tempy0=“10”))then
if(date0=“1001” and date1=“0010”)then
ov<='1';
else ov<='0';
end if;
elsif(date0=“1000” and date1=“0010”)then ov<='1';else ov<='0';end if;
elsif((mon0=“0001” and mon1=“0000”)or(mon0=“0011” and mon1=“0000”)or(mon0=“0010” and mon1=“0000”)
or(mon0=“0111” and mon1=“0000”)or(mon0=“1000” or(mon0=“0000” and mon1=“0001”)
or(mon0=“0010” and mon1=“0001”))then
if(date0=“0001” and date1=“0011”)then
ov<='1';
else ov<='0';
end if;
elsif(date0=“0000” and date1=“0011”)then
ov<='1';
else ov<='0';
end if;
end if;
end if;
end process u3;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;
and
mon1=“0000”)use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;use work.pac.all;entity h_m_s_time is
Port(clk0,clk1,ce : in std_logic;
sec0,sec1 : buffer std_logic_vector(3 downto 0);
lock : in std_logic_vector(2 downto 0);
up : in std_logic;
min0,min1 : buffer std_logic_vector(3 downto 0);
hour0,hour1 : buffer std_logic_vector(3 downto 0);
ov : out std_logic);end h_m_s_time;
architecture Behavioral of h_m_s_time is signal Ts0,Ts1,Tm0,Tm1,Th0,Th1:std_logic_vector(3 downto 0);signal clk:std_logic;begin
Ts0<=sec0;Ts1<=sec1;Tm0<=min0;Tm1<=min1;Th0<=hour0;Th1<=hour1;u1: process(lock,clk0,clk1)
begin
if(lock=“000” or lock=“001”)then
clk<=clk0;
else clk<=clk1;
end if;
end process u1;
u2: process(clk,lock)
begin
if rising_edge(clk)then
if(ce='1')then
if(lock=“000”)or(lock=“001”)or(lock=“111” and up='1')then
addsec_addmin(Ts0,Ts1,sec0,sec1);
end if;
if(lock=“111” and up='0')then
subsec_submin(Ts0,Ts1,sec0,sec1);
end if;
if(lock=“000” or lock=“001”)then
if(sec0=“1001” and sec1=“0101”)then
addsec_addmin(Tm0,Tm1,min0,min1);
end if;
if(sec0=“1001” and sec1=“0101” and min0=“1001” and min1=“0101”)then
addhour(Th0,Th1,hour0,hour1);
end if;
if(sec0=“1001” and sec1=“0101” and min0=“1001” and min1=“0101”
and hour0=“0011” and hour1=“0010”)then
ov<='1';
else ov<='0';
end if;
end if;
if(lock=“110” and up='1')then
addsec_addmin(Tm0,Tm1,min0,min1);
end if;
if(lock=“101” and up='0')then
subsec_submin(Tm0,Tm1,min0,min1);
end if;
if(lock=“101” and up='1')then
addhour(Th0,Th1,hour0,hour1);
end if;
if(lock=“101” and up='0')then
subhour(Th0,Th1,hour0,hour1);
end if;
end if;
end if;
end process u2;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity LED_disp is
Port(lock : in std_logic_vector(2 downto 0);
sec0,sec1,min0,min1,hour0,hour1 : in std_logic_vector(3 downto 0);
date0,date1,mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);
a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0));end LED_disp;
architecture Behavioral of LED_disp is begin process(lock,sec0,sec1,min0,min1,hour0,hour1,date0,date1,mon0,mon1,year0,year1)
begin
if(lock=“000”)then
a0<=sec0;a1<=sec1;b0<=min0;b1<=min1;c0<=hour0;c1<=hour1;
end if;
if(lock=“000”)then
a0<=sec0;a1<=sec1;b0<=min0;b1<=min1;c0<=hour0;c1<=hour1;
end if;
if(lock=“001”)then
a0<=date0;a1<=date1;b0<=mon0;b1<=mon1;c0<=year0;c1<=year1;
end if;
if(lock=“101”)then
a0<=“0000”;a1<=“0000”;b0<=“0000”;b1<=“0000”;c0<=hour0;c1<=hour1;
end if;
if(lock=“110”)then
a0<=“0000”;a1<=“0000”;b0<=min0;b1<=min1;c0<=“0000”;c1<=“0000”;
end if;
if(lock=“111”)then
a0<=sec0;a1<=sec1;b0<=“0000”;b1<=“0000”;c0<=“0000”;c1<=“0000”;
end if;
if(lock=“010”)then a0<=“0000”;a1<=“0000”;b0<=“0000”;b1<=“0000”;c0<=year0;c1<=year1;end if;if(lock=“011”)then
a0<=“0000”;a1<=“0000”;b0<=mon0;b1<=mon1;c0<=“0000”;c1<=“0000”;
end if;
if(lock=“100”)then
a0<=date0;a1<=date1;b0<=“0000”;b1<=“0000”;c0<=“0000”;c1<=“0000”;
end if;
end process;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;use work.pac.all;entity month_year is
Port(clk0,clk1,ce : in std_logic;
lock : in std_logic_vector(2 downto 0);
up : in std_logic;
mon0,mon1 : buffer std_logic_vector(3 downto 0);
year0,year1 : buffer std_logic_vector(3 downto 0));end month_year;
architecture Behavioral of month_year is signal Ty0,Ty1,Tm0,Tm1:std_logic_vector(3 downto 0);signal clk:std_logic;begin
Ty0<=year0;Ty1<=year1;Tm0<=mon0;Tm1<=mon1;u1: process(lock,clk0,clk1)
begin
if(lock=“000” or lock=“001”)then
clk<=clk0;
else clk<=clk1;
end if;
end process u1;u2:process(clk,ce)begin if rising_edge(clk)then
if(ce='1')then
if(lock=“000”)or(lock=“001”)or(lock=“011” and up='1')then
add_month(Tm0,Tm1,mon0,mon1);
end if;
if(lock=“011” and up='0')then
sub_month(Tm0,Tm1,mon0,mon1);
end if;
if(lock=“000” or lock=“001”)then
if(mon0=“0010” and mon1=“0001”)then
add_year(Ty0,Ty1,year0,year1);
end if;
end if;
if(lock=“010” and up='1')then
add_year(Ty0,Ty1,year0,year1);
end if;
if(lock=“010” and up='0')then
sub_year(Ty0,Ty1,year0,year1);
end if;
end if;
end if;
end process u2;
end Behavioral;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
package pac is
procedure add_year(oldyear0,oldyear1:in std_logic_vector;
signal newyear0:out std_logic_vector;
signal newyear1:out std_logic_vector);procedure add_month(oldmonth0,oldmonth1:in std_logic_vector;
signal newmonth0:out std_logic_vector;
signal newmonth1:out std_logic_vector);procedure sub_month(oldmonth0,oldmonth1:in std_logic_vector;
signal newmonth0:out std_logic_vector;
signal newmonth1:out std_logic_vector);procedure sub_year(oldyear0,oldyear1:in std_logic_vector;
signal newyear0:out std_logic_vector;
signal newyear1:out std_logic_vector);procedure Feb_add_day(oldday0,oldday1:in std_logic_vector;
ty0:in std_logic_vector(1 downto 0);
ty1:in std_logic;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure Feb_sub_day(oldday0,oldday1:in std_logic_vector;
ty0:in std_logic_vector(1 downto 0);
ty1:in std_logic;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure oddmonth_add_day(oldday0,oldday1:in std_logic_vector;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure oddmonth_sub_day(oldday0,oldday1:in std_logic_vector;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure evenmonth_add_day(oldday0,oldday1:in std_logic_vector;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure evenmonth_sub_day(oldday0,oldday1:in std_logic_vector;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure addsec_addmin(oldtime0,oldtime1:in std_logic_vector;
signal newtime0:out std_logic_vector;
signal newtime1:out std_logic_vector);procedure subsec_submin(oldtime0,oldtime1:in std_logic_vector;
signal newtime0:out std_logic_vector;
signal newtime1:out std_logic_vector);procedure addhour(oldhour0,oldhour1:in std_logic_vector;
signal newhour0:out std_logic_vector;
signal newhour1:out std_logic_vector);procedure subhour(oldhour0,oldhour1:in std_logic_vector;
signal newhour0:out std_logic_vector;
signal newhour1:out std_logic_vector);end pac;package body pac IS procedure add_year(oldyear0,oldyear1:in std_logic_vector;
signal newyear0:out std_logic_vector;
signal newyear1:out std_logic_vector)is
begin
if(oldyear0=“1001” and oldyear1/=“1001”)then
newyear0<=“0000”;newyear1<=oldyear1+'1';
else newyear0<=oldyear0+'1';
end if;if oldyear0=“1001” and oldyear1=“1001” then newyear0<=“0000”;
newyear1<=“0000”;end if;end add_year;
procedure add_month(oldmonth0,oldmonth1:in std_logic_vector;
signal newmonth0:out std_logic_vector;
signal newmonth1:out std_logic_vector)is
begin
if oldmonth0=“0010” and oldmonth1=“0001” then newmonth0<=“0001”;
newmonth1<=“0000”;
elsif oldmonth0=“1001” then newmonth0<=“0000”;
newmonth1<=oldmonth1+'1';else
newmonth0<=oldmonth0+'1';end if;end add_month;procedure sub_month(oldmonth0,oldmonth1:in std_logic_vector;
signal newmonth0:out std_logic_vector;signal newmonth1: out std_logic_vector)is begin
if oldmonth0=“0001”and oldmonth1=“0000”then
newmonth0<=“0010”;newmonth1<=“0001”;
elsif oldmonth0=“0000” and oldmonth1=“0001” then
newmonth0<=“1001”;newmonth1<= oldmonth1-'1';else newmonth0<=oldmonth0-'1';end if;if oldmonth0=“0000” and oldmonth1=“0000”then
newmonth0<=“0010”;newmonth1<=“0001”;
end if;
end sub_month;procedure sub_year(oldyear0,oldyear1:in std_logic_vector;signal newyear0: out std_logic_vector;signal newyear1: out std_logic_vector)is
begin if oldyear0=“0000”then
if oldyear1=“0000”then
newyear1<=“1001”;else newyear1<= oldyear1-'1';end if;newyear0<=“1001”;else newyear0<=oldyear0-'1';end if;end sub_year;procedure Feb_add_day(oldday0,oldday1:in std_logic_vector;
Ty0:in std_logic_vector(1 downto 0);
Ty1:in std_logic;
signal newday0: out std_logic_vector;
signal newday1: out std_logic_vector)is
begin
if oldday0=“1000”and oldday1=“0010”then
if((Ty1='0' and Ty0=“00”)or(ty1='1' and ty0=“10”))then
newday0<=oldday0 +'1';else newday0<=“0001”;newday1<=“0000”;end if;elsif oldday0=“1001” and oldday1=“0010”then
newday0<=“0001”;newday1<=“0000”;elsif oldday0=“1001” then
newday0<=“0000”;newday1<=oldday1+'1';else newday0<=oldday0+'1';end if;end Feb_add_day;
procedure Feb_sub_day(oldday0,oldday1:in std_logic_vector;
Ty0:in std_logic_vector(1 downto 0);
Ty1:in std_logic;
signal newday0: out std_logic_vector;
signal newday1: out std_logic_vector)is
begin
if(oldday0=“0000” or oldday0=“0001”)and oldday1=“0000”then
if((Ty1='0' and Ty0=“00”)or(ty1='1' and ty0=“10”))then
newday0<=“1001”;newday1<=“0010”;
else newday0<=“1000”;newday1<=“0010”;
end if;
elsif oldday0=“0000” and oldday1/=“0000”then
newday0<=“1001”;newday1<=oldday1-'1';else newday0<=oldday0-'1';end if;end Feb_sub_day;procedure oddmonth_add_day(oldday0,oldday1:in std_logic_vector;
signal newday0: out std_logic_vector;
signal newday1: out std_logic_vector)is
begin
if(oldday0=“0001” and oldday1=“0011”)then
newday0<=“0001”;newday1<=“0000”;
elsif oldday0=“1001”then
newday0<=“0000”;newday1<=oldday1+'1';
else newday0<= oldday0+'1';
end if;
end oddmonth_add_day;procedure oddmonth_sub_day(oldday0,oldday1:in std_logic_vector;
signal newday0: out std_logic_vector;
signal newday1: out std_logic_vector)is
begin
if(oldday0=“0001” or oldday0=“0000”)and oldday1=“0000” then
newday0<=“0001”;newday1<=“0011”;
elsif oldday0=“0000” and oldday1/=“0000” then
newday0<=“1001”;newday1<=oldday1-'1';
else newday0<= oldday0-'1';
end if;
end oddmonth_sub_day;procedure evenmonth_add_day(oldday0,oldday1:in std_logic_vector;
signal newday0: out std_logic_vector;
signal newday1: out std_logic_vector)is
begin
if oldday0=“0000” and oldday1=“0011” then newday0<=“0001”;
newday1<=“0000”;
elsif oldday0=“1001”then
newday0<=“0000”;
newday1<=oldday1+'1';
else newday0<=oldday0+'1';
end if;
end evenmonth_add_day;procedure evenmonth_sub_day(oldday0,oldday1:in std_logic_vector;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector)is begin
if(oldday0=“0000” or oldday0=“0001”)and oldday1=“0000”then
newday0<=“0000”;
newday1<=“0011”;elsif oldday0=“0000” and oldday1/=“0000”
then newday0<=“1001”;
newday1<=oldday1-'1';else
newday0<=oldday0-'1';
end if;end
evenmonth_sub_day;
procedure addsec_addmin(oldtime0,oldtime1:in std_logic_vector;
signal newtime0:out std_logic_vector;
signal newtime1:out std_logic_vector)is
begin
if
(oldtime0=“1001”)then
newtime0<=“0000”;
if(oldtime1=“0101”)then
newtime1<=“0000”;
else newtime1<=oldtime1+'1';
end if;
else newtime0<=oldtime0+'1';
end if;
end addsec_addmin;procedure subsec_submin(oldtime0,oldtime1:in std_logic_vector;
signal newtime0:out std_logic_vector;
signal newtime1:out std_logic_vector)is begin
if(oldtime0=“0000”)then
newtime0<=“1001”;
if(oldtime1=“0000”)then
newtime1<=“0101”;
else newtime1<=oldtime1-'1';
end if;
else newtime0<=oldtime0-'1';
end if;
end
subsec_submin;procedure addhour(oldhour0,oldhour1:in std_logic_vector;
signal newhour0:out std_logic_vector;
signal newhour1:out std_logic_vector)is begin
if(oldhour0=“1001”)then
newhour0<=“0000”;
newhour1<=oldhour1+'1';
else newhour0<=oldhour0+'1';
end if;
if oldhour0=“0011” and oldhour1=“0010”then
newhour0<=“0000”;newhour1<=“0000”;
end if;
end
addhour;procedure subhour(oldhour0,oldhour1:in std_logic_vector;
signal newhour0:out std_logic_vector;
signal newhour1:out std_logic_vector)is begin if oldhour0=“0000” then
newhour1<=oldhour1-'1';newhour0<=“1001”;
else newhour0<=oldhour0-'1';
end if;
if oldhour0=“0000” and oldhour1=“0000”then
newhour0<=“0011”;newhour1<=“0010”;
end if;
end
subhour;end pac;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity second_wave is
Port(f1000 : in std_logic;
second_wave1 : buffer std_logic);end second_wave;
architecture Behavioral of second_wave is signal cnt:std_logic_vector(8 downto 0);begin
process(f1000,cnt)
begin
if rising_edge(f1000)then
if(cnt=“111110011”)then
cnt<=“000000000”;second_wave1<=not second_wave1;
else cnt<=cnt+'1';
end if;
end if;
end process;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity settime is
Port(hour1,hour0,min1,min0,sec1,sec0 : in std_logic_vector(3 downto 0);
mytime,run : in std_logic;
result : out std_logic);end settime;
architecture Behavioral of settime is signal dhour1,dhour0,dmin1,dmin0,dsec1,dsec0:std_logic_vector(3 downto 0);begin p0:process(mytime)
begin
if mytime='1'then
dhour1<=hour1;
dhour0<=hour0;
dmin1<=min1;
dmin0<=min0;
dsec1<=sec1;
dsec0<=sec0;
end if;
end process p0;p1:process(run)
begin if run='1'then
if hour1=dhour1 and hour0=dhour0 and min1=dmin1 and min0=dmin0 and sec1=dsec1 and sec0 =dsec0 then
result<='1';
else result<='0';
end if;else result<='0';end if;
end process p1;end Behavioral;
第三篇：51单片机c语言电子钟(已加入调时、闹铃、整点报时功能)
51单片机c语言电子钟（已加入调时、闹铃、整点报时功能）
效果图：
程序如下：
//51单片机c语言电子钟（已加入调时、闹铃、整点报时功能）
//WHJWNAVY 2011/10/14
#include
P2=0XDF;P0=dispcode[10];//间隔符-delay(1);
P2=0XBF;
P0=dispcode[shi%10];//时个位 delay(1);P2=0X7F;P0=dispcode[shi/10];//时十位 delay(1);}
if(P1_6==0)//设定时 { delay(30);if(P1_6==0){ shi++;if(shi==24){ shi=0;} } delay(250);} if(P1_7==0)//设定分 { delay(30);
if(P1_7==0){ fen++;if(fen==60){ fen=0;} } delay(250);}
if((hour==shi)&(minite==fen)&(seconde==0))//闹铃时间到，报警十次。{ for(bjcs=0;bjcs<10;bjcs++){ P1_5=0;delay(500);P1_5=1;delay(500);} } }
/*主函数*/ void main(void){ P1=0XFF;TMOD = 0x11;//time0为定时器，方式1 TH0=0x3c;//预置计数初值,50ms TL0=0xb0;EA=1;//总中断开
ET0=1;//允许定时器0中断 TR0=1;//开启定时器0 while(1){ keyscan();//按键扫描 dingshi();//定时闹钟 zhengdian();//整点报时 display();//显示时间 } }
void timer0(void)interrupt 1 //定时器0方式1，中断一次 { TH0=0x3c;//手动加载计数脉冲次数
50ms
TL0=0xb0;TMOD=0x11;mstcnt++;//用于计算时间，每隔50ms加1 if(mstcnt==20)//mstcnt满20即为一秒 { seconde++;//秒+1 time_pro();//时间处理
mstcnt=0;//对计数单元的清零，重新开始计数 } }
第四篇：认识整点教案
大班数学《认识整点》
赵海凤
活动目标：、使幼儿认识时钟，能叫出名称，基本掌握钟面的主要结构。2、使幼儿知道时针、分针、能正确辨认整点。、培养幼儿的观察力和操作能力，使幼儿建立初步的时间概念。
活动准备：
课件《认识整点》、实物大钟一个、小钟若干、钟面若干
一、预备活动。
走线，线上游戏：听音乐一个跟着一个走随老师做动作。
二、集体活动。
1、以谜语 一张大圆脸，没腿也没嘴。没腿会走路，没嘴能报时。引入活动，请大家猜猜是什么？教师出示挂钟，提问：“它叫什么？家里还有哪些钟（大座钟，催我们早早起的小闹钟，还有人们为了携带方便，将钟做得很小，戴在手上，叫手表）？钟的作用是什么？（时钟不停地走动，为人们显示时间，人们按时钟上的时间来进行工作、学习和工作。
2.教师出示大钟，请幼儿观察钟面。钟面上有1—12的数字，有两根指针，钟上的数字“12”在上面，“6”在下面，并教幼儿认识“时针”和“分针”的名称。
2.针兄弟要在圆形跑到上比赛跑，帮助幼儿认识较短的时针和较长的分针，探索分针和时针的运动关系。教师慢慢拨钟，引导幼儿观察分针和时针的运动。让幼儿说出：分针跑得快，时针跑得慢。通过拨钟，引导幼儿认识整点。教师将时针分针都拨在“12”上，然
后将长针转一圈，让幼儿注意短针有什么变化（走了一大格或走了一个数字），教师反复拨几次，使幼儿明白长针（分针）每走一圈，短针（时针）就走一个字，这就是一个小时。
3、教师继续拨长针。边拨边告诉幼儿当短针（时针）正指向某一个数字，长针（分针）正指向某一个数字，长针（分针）正指向12时就表示“X”点钟。边拨边和幼儿齐说：“一点钟，两点钟，三点钟..........直到十二点钟”（即：两针再次重合）为止。
4、引导幼儿在钟面上拨出各个钟点。老师演“狼”说几点，小羊就拨几点，请老狼巡视看钟。小羊拨好了钟就定住，老狼看时间拨对了的不吃，拨错了就吃小羊。
5、教师根据幼儿拨钟情况总结，没个时间段在做什么，早上7点起床，上午9点上课，中午12点吃午餐，下午5点放学，晚上8点睡觉。教育幼儿从小做到按时间进行各种活动，珍惜时间，上学不能迟到，放学时不能在路上贪玩。
三、游戏活动：老狼老狼几点钟。
教师手拿1－12点钟面卡片走在前面。幼儿跟在“老狼”后面边走边问：“老狼老狼几点钟”？“老狼”举起1点钟的卡片并回答：“1点钟”。...........当“老狼”回答“天黑了”时，其他幼儿必须快速回到座位上安静下来，最后一个回到座位上的幼儿就被“老狼”“吃掉”，游戏反复进行。
四、结束部分
知识拓展，引导幼儿了解古代的计时方法。
第五篇：认识整点和半点
认识整点和半点 活动目标：
1、幼儿在回忆已有经验的基础上，通过对钟面的观察与操作了解秒针、分针、时针的运行关系。
2、认识整点、半点及的读法及记录方法。
3、在活动中诱发幼儿形成遵守时间与爱惜时间的良好习惯。
活动准备：
1、教具：有关各种时钟的幻灯片;时钟一面，可活动钟面一只;表示7、8、9、10点钟的钟面各一只，时间记录卡各一张。
2、学具：幼儿观察记录表每人一份，活动钟面每人一份;实物时钟4只。
活动过程：
一、调动已有经验，回忆相关知识。
1、前段时间我们小朋友和老师一起做了有关时钟的调查，知道时钟有好多好多种。现在请你看看老师从网上下载的钟，看看你认识它吗?
2、依次出示幻灯片，幼儿讲名称。
3、刚才我们所见到的只是时钟家族的一部分，它可能还有其他的种类，我们以后再来探讨。
4、上次我们已经认识过钟面，来告诉大家，最长的针叫(秒针)，有点长的针叫(分针)，最短的针叫时针。钟面上一共有多少个数字(12)，最上面的是数字12，然后依次是1、2……11。请你好好回忆一下，时钟里的指针是朝哪一个方向走的?(1……12)对了，这样的方向就叫顺时针方向。
二、交流调查表，说说自己在什么时间，正在干什么?
1、小朋友们说的真好，那你知道我们人为什么要使用钟吗?
2、钟与我们人的生活有着密切的关系，前几天我们小朋友已经做过了一个调查，将自己活动的时间记录了下来，现在请你拿出自己的调查表，说说你在什么时间在干什么?你只要说出长针在几，短针在几的时候，你在干什么?好我们先自己说。
3、谁愿意上来说给大家听。(请3—4个小朋友上来说)。
4、说的真好，钟面上的指针在不停的发生着变化，它们在运行中有什么关系呢?
5、老师为你们准备了几个时钟，请你看看里面有几根指针，(两根)你猜猜看是哪两根针呢?(分针与时针)，那秒针在哪儿呢?听(滴答)声就是秒针在跑。那他们两在运行时有什么关系呢?下面请我们小朋友们去玩一玩，看看他们之间到底有什么秘密?注意，拨指针的时候一定要按照顺时针方向拨。
6、说说看，你们都发现了什么?说的真好，分针走一圈，时针走一格，这就表示一个小时。
7、那么长针、短针指着的数字又是表示几点钟呢?别急，老师来向你们介绍。
三、认识整点、半点以及它们的记录方法。
1、好，先请你们听一个好听的故事。
2、教师有表情的讲述故事《小明秋游》，边讲边出示相关时间的钟面。
3、讲述后提问：
1)、小明去秋游了吗?为什么没去成?
2)、他该几点钟起床，他是几点钟起床的?
3)、小明到幼儿园是几点钟了?
4)、他为什么会迟到，他是几点钟睡觉的?
课后反思：
优点：
1.创设情景，激发兴趣。在课的开始部分利用谜语和色彩鲜艳的多媒体课件激发了幼儿的兴趣。
2.小组合作，探究新知。在活动中，我采取了小组合作学习的形式，让让幼儿自主学习，通过观察、比较、操作、交流等多种形式，调动幼儿多种感官进行合作学习，培养合作意识，让幼儿体验成功的快乐。
3.游戏化教学，符合幼儿认知规律。在活动中，我运用了多种游戏形式，如：敲一敲、师幼竞赛、拿票坐车去玩等，在游戏中幼儿进一步认识了钟表，让幼儿在游戏中获得了发展。
4.教具、学具准备充分，钟面和实物闹钟达到人手一份，为幼儿创造了丰富的操作材料。
不足：
1.幼儿认真倾听的习惯还有待加强培养。
2.教师的语言要注意儿童化。
点击咨询 